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Learn how to change Xilinx IP core to Altera, understand transceiver differences, test protocols in Aurora, and troubleshoot potential issues. Step-by-step tutorial with examples and detailed explanations.
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CDC Merger Liu Shih-Min ; Alan, Teng; C.H. Wang NUU, Taiwan
Outline • Aurora IPcorefiles • Change Xilinx IPcore to Altera • Transmit speed • Transceiverdifference • Test over • In test • problem
Aurora IPcorefiles • Aurora IPcorefiles • ./SRC • Auroraprotocolcore files • ./example_design • User interfaceexample files
Change Xilinx IPcore to Altera • Need remove and replace component • Need remove • I/O buffer • Need replace • FD、FDR、SRL16...etc. • Transceiver、PLL
Transmit speed • Xilinx : linerate • Altera : effective datarate • Transmit how many bit per-second
linerateand datarate • Aurorause 8b10bencoder/decoder,so 8 bits data will use 10 bits space, and datarate will be linrate*0.8. • For example,linerate is5Gbps the datarate is 5Gbps*0.8 = 4Gbps
Transceiverdifference • Xilinx • transmit and receiveuse same clock • support Auroraprotocolfunction • Altera • transmit and receive use different clock • Support part of Auroraprotocolfunction
Xilinx and Altera transceiver structure: transmitter XILINX ALTERA
Xilinx and Altera transceiver structure: receiver XILINX ALTERA
Test over • SP6 Aurora 3.125G in Altera Stratix4 • SP6 Stratix-4 • Virtex6 Stratix-4 • VT6 Aurora 3.125G in Altera Stratix4 • VT6 Stratix-4 OK OK
In test • VT6 Aurora 5G in Altera Stratix4 • Change IPcore complete • VT6and Stratix4transceivertest complete • Loopbackis in test • VT6 Stratix4test is in test
Problem in 5G test • Altera transceiver can’t setup 5Gbps and 16bit width directly • Successful solve • Receive data is incorrect • Successful solve • 5G Coreon Stratix4 still can’t work • When receive the initial sequence, the core is no responce.