Preliminary Results of the DS92LV18 Rad Tolerance Tests

1. Preliminary Results of the DS92LV18 Rad Tolerance Tests A. Aloisio, R. Giordano Physics Dept. - University of Napoli “Federico II” and INFN Sezione di Napoli, Italy email: aloisio@na.infn.it, rgiordano@na.infn.it

2. Outline • On-detector SerDes in the ETD framework • DS92LV18: protocol and loss-of-locks • Test-bench for DS92LV18 • Test facility and conditions • Results • Conclusions and future work Raffaele Giordano SuperB Workshop, Isola d'Elba 2010

3. SerDes in rad enviroments Layout by D. Breton LNF, Dec.09 • FCTS links: • Timing & Clock • Commands & Controls • config data • DATA links: • Read-out payload • DS92lv18: • Fixed latency • 1.2 Gbit/s • Receives from FCTS crate • Transmits to Trigger Primitives B-Type Links C-Type Links FCTS link Tight latency requirements DS92lv18 Data link No tight latency requirements DS92lv18 or TLK2711A Raffaele Giordano SuperB Workshop, Isola d'Elba 2010

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5. Fake locks could be achieved with too-deterministic data-patterns Raffaele Giordano SuperB Workshop, Isola d'Elba 2010

6. Raffaele Giordano SuperB Workshop, Isola d'Elba 2010

7. DS92LV18 Test board Diff. impedance 120 W • High speed I/O and clocks on SMA connectors with controlled impedance • RX, TX, Controls busses on parallel connectors with matched length and controlled impedance • Static control programming enabled via jumpers • Separate supplies for analog, digital, PLL with sense (4-wire scheme) • Current sensing on each supply • 10 layer PCB, separate power and ground planes TX clk TX out RX in Reference clk Recovered Clock 57 W Raffaele Giordano SuperB Workshop, Isola d'Elba 2010

8. Tektronix DTG5334 18 2 8 18 Controls RX Data out DS92LV18 Test Bench Ethernet link Ethernet link BRIDGE RS-232 link XILINX ML505 PC logging all the data on the hard-drive (errors, lock time…) Clock Generator FPGA Clk RX Reference Clk Recovered Clk TX Clk TX Data in Ethernet link Power Analyzer & Logger Controls RX Serdes TX Serdes LeCroy SDA600A 3.3V Power AGILENT N6705A Raffaele Giordano SuperB Workshop, Isola d'Elba 2010

9. FPGA setup Console I/O Parallel I/O Clock output • Data pattern stored in the FPGA firmware • Testing the SerDes RX section • Drives the SerDes receiver input with serial stream, emulating the DS92LV18 protocol • Receives DS92LV18 parallel output • Cross check received data vs. transmitted • Logs errors and loss-of-locks • Lock time measurements • Testing the SerDesTX section • Drives the SerDes transmitter input with parallel data • Receives the SerDes serial stream, emulating the DS92LV18 protocol • Cross check received data vs. transmitted • Logs errors • Controls section • Programs controls bits • Console • Status and errors are logged on a console handle by an embedded micro XILINX ML505 Virtex5 – XC5VLX50T Clock input GTPdiff. I/O • TX and RX sections of the SerDes are tested independently and simultaneosly Raffaele Giordano SuperB Workshop, Isola d'Elba 2010

10. Test Time Slicing • Test divided in 10-s units • Test Log file • Each unit consists of 3 time slices: • BER test with logging (tx/rx errors and loss-of-lock) ~ 9.5 seconds • Lock time measurements ~ 100 ms • Static currents measurement (powerdown) ~400 ms • This modularity allowed us to measure currents (PLL,digital and analog) and lock time vs time • Same test will be used for TID Time Unit N Time Unit N+1 Raffaele Giordano SuperB Workshop, Isola d'Elba 2010

11. Link and Data Error Log • Monitor Errors in the link payload and Lock flag state variations • Each data error and loss-of-lock is time-stamped with clock period resolution • Log expected and wrong word => we know exactly which bit flipped Lock Status Time Stamp Relative to TU Error on Rx Time Stamp Corrupted 11011100111100011 Expected 11011100101100011 Single Bit Error Raffaele Giordano SuperB Workshop, Isola d'Elba 2010

12. Test Beam Basic Facts beam spot • Proton accelerator at INFN Laboratori Nazionali del Sud (LNS) • CATANA beam line • 60-MeV protons • Beam spot diameter 25 mm • During our test • Ibeam ~ 500 pA • Test time = 6 ks • Total dose in Si ~ 4 kGy • Total Nprotons ~ 5·1013 • Vcc = 3.45 V (highest voltage => worst condition) • fclock = 62.5 MHz Front view DS92LV18 Test-board Back view FPGA board 1/F = 10-13 cm2 Raffaele Giordano SuperB Workshop, Isola d'Elba 2010

13. Test Results stx= 2.5 10-12 cm2 • # Tx errors = 25 (both single and multiple bit errors) • # Rx errors = 1 (single bit error) • # Loss-of-locks = 6, re-lock in 800 ns • No SELs (chip wasn’t damaged) • No SEFIs (chip did not power-down due to SEU) • After irradiation, we left the system under measurement for 8 hours, no error observed srx= 10-13 cm2 slink= 6 10-13 cm2 Order of magnitude agrees with previous studies on similar chip DS65LV1023/1224 Raffaele Giordano SuperB Workshop, Isola d'Elba 2010

14. Errors Anatomy Consecutive time stamps • Tx • Single bit errors • Multiple bit errors • Burst errors (up to 4 consecutive corrupted words) • Parity is not enough • Rx • Single bit errors • Loss-of-locks Raffaele Giordano SuperB Workshop, Isola d'Elba 2010

15. A Few Remarks • Loss-of-locks • Defined a strategy to recover within a deterministic time frame from a loss-of-lock • It could be used in SuperB, but we need a return channel • This conflicts with using the return path for trigger primitives • Radiation • Had to leave tested and control boards in hot room • All cabling (power, serial, parallel) is now activated and has to be replaced • Can not go to higher doses in that facility, radioprotection issues Raffaele Giordano SuperB Workshop, Isola d'Elba 2010

16. Jitter Issues on Clock Recovery PRWS pattern • TIE histograms of clock recovered from DS92LV18 (taken before irradiation) • PRWS Random jitter of the order of 25ps • TIE histo distorted with SYNC pattern (150ps deterministic jitter) SYNC pattern Raffaele Giordano SuperB Workshop, Isola d'Elba 2010

17. Successfully made the first radiation test for SEU on DS92LV18 Good agreement with previous studies on similar chips We monitored currents, data errors and link failures, lock-time as function of time (and therefore absorbed dose) We found both data errors and link failures (loss-of-locks) We found multiple bit errors Basically everything was within 5cm of the beam trajectory is now activated => need replacement for cabling Conclusions… Raffaele Giordano SuperB Workshop, Isola d'Elba 2010

18. …Remarks and… • Emulation on FPGA completed and tested in-the-field for both Serializer and Deserializer • We handled the problem of a loss-of-lock and defined a lol-recovery-protocol Raffaele Giordano SuperB Workshop, Isola d'Elba 2010

19. …Future Work • Analyze trend of lock time and currents (PLL, Analog, Digital) with absorbed dose • Perform longer test and test other samples (all results refer to the only chip tested so far) • Test DS92LV18 for Total Integrated Dose (probably at ENEA Casaccia, need money for this) • Qualify both TID and SEU radiation hardness of Texas TLK2711A (candidate for data links) Raffaele Giordano SuperB Workshop, Isola d'Elba 2010

20. Back-up Slides Raffaele Giordano SuperB Workshop, Isola d'Elba 2010

21. Quick Facts • Tx Errors = 21 single and 4 multiple bit errors • rSi = 2.3 g/cm3 • (dE/dx)proton at 60MeV in Si = 1.8 MeV/mm (or 600 keV in 300 mm) • s = (1 / F) * nerrors Raffaele Giordano SuperB Workshop, Isola d'Elba 2010

22. Seed Clock (frefclk ±5%) C & B-Type Links (tested) FCTS Crate • National DS92LV18 has fixed-latency, candidate to be radiation tolerant • Line rate at 1.25 Gbps, limited by DS92LV18 • Successfully completed emulation of DS92LV18 protocol inside FPGA • Successfully completed tests for FPGA-to-DS92LV18 and DS92LV18-to-FPGA transmission Trigger Primitives Raffaele Giordano SuperB Workshop, Isola d'Elba 2010

23. from National Semi • SEL • SEFI TID Raffaele Giordano SuperB Workshop, Isola d'Elba 2010 SuperB Workshop - SLAC, Oct.09 23