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COE4DI4 Engineering Design and VHDL

This text explains the process of engineering design, from defining specifications to prototype implementation, using VHDL for digital hardware design. It covers concept development, functional simulation, physical mapping, timing simulation, and CAD tools.

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COE4DI4 Engineering Design and VHDL

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  1. COE4DI4Engineering Design and VHDL

  2. Definition of Engineering Design • The process of devising a system, component, or process to meet desired needs

  3. Required product Design specifications Initial design Simulation Redesign No Design correct? Yes Prototype implementation Make corrections Yes Testing Minor errors? No No Meets specifications? Yes Finished product The development process

  4. Design Process • Define specifications: essential features of the product are identified. • Specifications must be tight enough to ensure that the developed product will meet the general expectations, but not be unnecessarily constraining. • Initial design: is generated from the design specifications • This step is usually performed by a human designer. • It requires considerable design experience and intuition.

  5. Design Process • Simulation: CAD tools are used to simulate the behavior of the initial design to determine whether the obtained design meets the required specifications. • If errors are found appropriate changes are made and verification is repeated through simulation. • Usually all except subtle problems are discovered in this way. • When simulation indicated that the design is correct, a prototype of the product is constructed.

  6. Design Process • The prototype is thoroughly tested for conformance with the specifications. • Minor errors are often eliminated by making small corrections directly on the prototype. • In the case of large errors, it is necessary to redesign the product.

  7. Design of digital hardware

  8. Design concept A Partition B Design one block Design one block C Design interconnection between blocks Functional simulation of complete system No Correct? D Yes Physical mapping Timing simulation No Correct? Yes Implementation Figure 1.6Design flow for logic circuits

  9. Implementation Build prototype Testing Modify prototype Yes No Correct? Minor errors? No Yes Finished Go to A, B, C, or D Development of a complex digital hardware

  10. Design of digital hardware • A common way of dealing with complexity in digital hardware is to partition the circuit into smaller blocks and design each block separately. • Having successfully designed all blocks, the interconnection between blocks must be defined. • The complete circuit is simulated and errors are corrected • Errors caused by incorrect connections: connections are redefined (path C) • Some blocks have not been designed correctly: erroneous blocks are redesigned (path B) • Some functionality missing: incorrect partitioning (path A)

  11. Design of digital hardware • Physical mapping: physical location of each chip on the board and wiring pattern • CAD tools are relied on • Does the physical layout affect the performance of the circuit (even though the functional behavior of complete system is correct)? • Physical wiring introduce resistance and capacitance. It may have an impact on the speed of operation. • Timing simulation is used to check the performance of the circuit after wiring.

  12. Design of digital hardware • Having completed timing simulation a prototype of the circuit is implemented. • The prototype is tested. • Minor errors are corrected on the prototype. • Large problems require a redesign.

  13. CAD tools • A CAD system has tools for performing the following tasks: • Design entry • Initial synthesis • Functional simulation • Logic synthesis and optimization • Physical design • Timing simulation • Chip configuration

  14. Design conception DESIGN ENTRY Truth table Schematic capture VHDL Simple synthesis Translation Merge INITIAL SYNTHESIS TOOLS Boolean equations Functional simulation No Design correct? Yes Logic synthesis, physical design, timing simulation The first stages of a CAD system

  15. Design conception Design entry, initial synthesis, and functional simulation Logic synthesis/optimization Physical design Timing simulation No Design correct? Yes Chip configuration A complete CAD system

  16. CAD tools • The starting point in the process of designing a digital circuit is the conception of what the circuit is supposed to do and the formulation of its general structure. • This step is done manually. The rest is done by CAD tools.

  17. CAD tools • Design entry: a description of the circuit being designed should be entered into CAD system • Different ways of doing this: • Truth tables • Schematic capture • Hardware description languages • Initial synthesis: produces a network of logic gates

  18. CAD tools • Functional simulation: is used to verify the functionality of the circuit based on input provided by the designer • This simulation is performed before any optimization and propagation delays are ignored. • Goal: validate the basic operations of the circuit

  19. CAD tools • Logic synthesis and optimization: produces an equivalent but better circuit • The measure of what makes one circuit better depends on the needs of a design project and the technology chosen for implementation

  20. CAD tools • Physical design (layout synthesis): how to implement the circuit in the target technology • This step consists of placement and routing • Placement: where in the target device each logic function in the optimized circuit will be realized • Routing: which wires in the chip are to be used to realize the required interconnections

  21. CAD tools • Timing simulation: determines the propagation delays that are expected in the implemented circuit • Timing simulation: ensures that the implemented circuit meets the required performance • Some of timing errors can be corrected by using the synthesis tool • If the logic synthesis tool cannot resolve the timing problem, it is necessary to return to the beginning of the design flow to consider other alternatives • Final step: configure the target chip to implement the circuit

  22. Summary • Design and development process • Design of digital hardware • CAD tools

  23. Design concept Initial design Simulation Redesign No Design correct? Yes Successful design The basic design loop

  24. Introduction to VHDL • VHDL (VHSIC Hardware Description Language) is a language used to express complex digital systems concepts for documentation, simulation, verification and synthesis. • VHDL is a language widely used to model and design digital hardware. • Design tools translate a design described in VHDL into actual working system in various target technologies very fast and reliable. • VHDL is supported by numerous CAD tools and programmable logic vendors. • VHDL was first standardized in 1987 in IEEE 1076-1987 • An enhanced version was released in 1993

  25. Introduction • VHDL has had an enormous impact on digital system design and methodology • VHDL promotes a hierarchical top-down design • It takes the designer away from low level details (e.g., transistors and gates) to higher levels (system description) • VHDL allows design entry in different levels: • Exp: part of the design at behavioral level and part at the level of netlist • Conventional programming languages: sequential operations • VHDL is designed to model parallel operations (concurrent events)

  26. Introduction • Advantages of using VHDL for design: • Shorter design time and reduced time to market • Reusability of already designed units • Fast exploration of design alternatives • Independence of the target implementation technology • Automated synthesis • Easy transportability to other design tools • Parallelization of the design process using a team work approach

  27. Introduction • VHDL consists of several parts organized as follows: • Actual VHDL language specified by IEEE • Some additional data type declarations in the standard package called IEEE standard 1164 • A WORK library reserved for user’s designs • Vendor packages with vendor libraries • User packages and libraries

  28. VHDL design • A VHDL design consists of several design units (building blocks) • Each design unit can be compiled into a library for subsequent simulation or use in other designs • Four source design units that can be compiled are: • Entity: describes the design’s interface signals • Architecture: describes design’s behavior • Package: stores frequently used specifications such as data types • Configuration: selects a variation of a design from a library

  29. VHDL design • Two built-in libraries are WORK and STD • VHDL source design units are complied into WORK library • The ieee library is a storage place for IEEE standard design units • User can create other libraries

  30. VHDL design (Library) • To use a library it should be declared (made accessible to the design): • Exp: library ieee • WORK library is implicitly accessible in all designs and does not need to be declared • Complied units in a library can be accessed via a use statement • Syntax: • use library_name.package_name.item_name • use library_name.item_name • Exp: use ieee.std_logic_1164.all

  31. VHDL design (Package) • Next level of hierarchy within a library is a package. • Package is created to store common data types, constants and complied designs that will be used in more than one design (reusability) • A package is used for: • Type and subtype declaration • Constant declaration • Function and procedure declaration • File declaration

  32. VHDL design (Package) • All vendors provide a package named STANDARD in a predefined library named STD. This package defines useful data types • A use clause allows access to a package in a library • Syntax: • use library_name.package_name.item_name • use library_name.item_name • Exp: use ieee.std_logic_1164.all • No useclause is required for the package STANDARD (it is default)

  33. Entity & Architecture • A VHDL design is a paring of an entity declaration and an architecture body. • Entity declaration: describes the design I/O and my include parameters used to customize an entity • Architecture body: describes the function of a design • Each I/O signal in an entity declaration is referred to as a port • A port is a data object • Like other data objects it can be assigned values and used in expressions

  34. Entity & Architecture • Each port must have a name, a direction (mode) and a data type. • Mode: describes the direction in which data is transferred through a port • Example: port (a, b : in bit_vector(3 downto 0); equals: out bit); • Mode can be one of 4 values: in, out, inout, or buffer • In: data flows only into the entity. The driver of the port is external (e.g., clock input) • Out: data flows only from its source (inside the entity) to the port • Note: out does not allow feedback

  35. Entity & Architecture • Buffer: for internal feedback (to use a port also as a driver within the architecture) • Buffer is used for ports that must be readable inside the entity, such as the counter outputs (the present state of a counter must be used to determine its next stage • Inout: allows data to flow into or out of the entity. It also allows for internal feedback • Mode inout can replace any of the other modes

  36. Entity & Architecture • In addition to specifying modes for ports, you must declare data types for ports • The most important data types in VHDL are Boolean, bit, bit_vector, and integer • The most useful types provided by the IEEE std_logic_1164 package is std_logic and array of this type. • For simulation and synthesis software to process these types, their declaration must be made visible to the entity by way of library and use clauses

  37. entity eqcomp4 is port (a, b : in bit_vector(3 downto 0); equals: out bit); end eqcomp4; architecture dataflow of eqcomp4 is begin equals <=‘1’ when (a=b) else ‘0’; end dataflow;

  38. ANDGATE A C B VHDL design (Entity) • Design entity defines a new component name, its input/output connections and describes parameterized values. • Entity represents the I/O interface (external connections) of a component. entity andgate is port (a,b : in bit; c: out bit); end andgate

  39. VHDL design (Entity) • Syntax for an entity declaration: entity entity_name is [generic (list-of-generics-and-their-types);] [port (list-of-interface-port-names-and-their-types);] [begin entity-statements] end [entity] entity-name; • Generic list: allows additional information to pass into an entity • Useful for parameterization of the design

  40. VHDL design (Architecture) • An architecture specifies the behavior, interconnections and components of an entity. • Architecture defines the function of an entity • It specifies the relationship between inputs and outputs. • VHDL architectures are categorized in style as: • Behavior • Dataflow • Structural • A design can use any or all of these styles.

  41. VHDL design (Architecture) • Behavior: the behavior of the entity is expressed using sequentially executed procedural code (very similar to programming languages like C) • Sometimes called high-level description • Rather than specifying the structure of a circuit, you specify a set of statements that when executed in sequence model the behavior of the entity. • Uses process statement and sequential statements (the ordering of statements inside process is important)

  42. VHDL design (Architecture) • Dataflow: specifies the functionality of the entity (the flow of information) without explicitly specifying its structure • It specifies how data will be transferred from signal to signal and input to output without the use of sequential statements. • No use of process or sequential statements • Structural: an entity is modeled as a set of components connected by signals • Components are instantiated and connected together

  43. -- a four bit equality comparator library ieee; use iee.std_logic_1164.all; entity eqcomp4 is port (a, b : in std_logic_vector(3 downto 0); equals: out std_logic); end eqcomp4; architecture behav of eqcomp4 is begin comp: process (a, b); begin if a=b then equals <= ‘1’; else equals<=‘0’; end if; end process comp; end behav;

  44. library ieee; use iee.std_logic_1164.all; entity eqcomp4 is port (a, b : in std_logic_vector(3 downto 0); equals: out std_logic); end eqcomp4; architecture dataflow of eqcomp4 is begin equals <=‘1’ when (a=b) else ‘0’; end dataflow;

  45. library ieee; use iee.std_logic_1164.all; entity eqcomp4 is port (a, b : in std_logic_vector(3 downto 0); equals: out std_logic); end eqcomp4; architecture bool of eqcomp4 is begin equals <= not(a(0) xor b(0)) and not(a(1) xor b(1)) and not(a(2) xor b(2)) and not(a(3) xor b(3)) ; end bool;

  46. library ieee; use iee.std_logic_1164.all; library altera; use altera.quartus.all; entity eqcomp4 is port (a, b : in std_logic_vector(3 downto 0); equals: out std_logic); end eqcomp4; architecture struct of eqcomp4 is signal x: std_logic_vector(0 to 3); begin u0: xnor port map (a(0),b(0),x(0)); u1: xnor port map (a(1),b(1),x(1)); u2: xnor port map (a(2),b(2),x(2)); u3: xnor port map (a(3),b(3),x(3)); u4: and4 port map(x(0), x(10, x(2), x(3), equals); end struct;

  47. VHDL • VHDL does not assume any precedence of operation and therefore parentheses are necessary in VHDL expressions. • <= is the signal assignment operator in VHDL

  48. x 1 x 3 f x 2 g x 4 Logic circuit for four-input function

  49. Whenever there is an event on x1, x2, x3, the expression on the right side is evaluated and the value appears on f and/or g. Figure 2.30 VHDL code for a four-input function

  50. Example • The signal assignments in the previous example are concurrent statements. • Concurrent statements are order independent.

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