1 / 18

Design and Fabrication of a Radiation-Hard 500-MHz Digitizer Using Deep Submicron Technology

Proposal for a radiation-hard digitizer chip with high bandwidth and resolution for NLC beam position monitoring at high-energy physics facilities. The design utilizes deep-submicron technology to achieve 11-bit resolution, 500 MHz bandwidth, and 2 G samples/s. The project aims to address the digitization needs of multi-bunch BPM systems, offering easy access for testing and maintenance without requiring costly shielding. The plan includes completing the design, layout, and testing of the digitizer chip, with radiation hardness tests and continued system development.

rogersr
Download Presentation

Design and Fabrication of a Radiation-Hard 500-MHz Digitizer Using Deep Submicron Technology

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Design and Fabrication of a Radiation-Hard 500-MHz DigitizerUsing Deep Submicron Technology July 29, 2004 R. Kass The Ohio State University K.K. Gan, M.O. Johnson, R.D. Kass, A. Rahimi, C. Rush The Ohio State University S. Smith SLAC US LC Conference

  2. Presentation Outline lNLC Requirements lADC (“digitizer”) Design lProgress Report lPlans US LC Conference

  3. Beam Position Monitor Requirements at NLC lNLC will collide 180-bunch trains of e- and e+: nbunch spacing: 1.4 ns nalignment of individual bunches in a train: < 1 mm nBPM determines bunch-to-bunch misalignment ]high bandwidth kickers bring the train into better alignment on next machine cycle ]multi-bunch BPM system with digitizers: 11-bit effective resolution 500 MHz bandwidth 2 G samples/s US LC Conference

  4. Requirements of NLC Digitizers important to demonstrate feasibility of high speed/resolution digitizers ]redesign of low level RF technology is needed without the digitizers US LC Conference

  5. Proposal lDesign a digitizer chip using deep-submicron technology (0.25 mm) nuse enclosed layout transistors and guard rings ☺radiation hard: > 60 Mrad ☺no need for costly shielding and long cables ☺easy access to electronics for testing and maintenance lExtensive experience in chip design using Cadence ndesigned radiation-hard chips for CLEO III, ATLAS, CMS lWhy OSU is interested? nhelp to solve a challenging NLC problem npotential applications in HEP lHoltkamp Committee rankings: 2 on scale of 1 to 4 (lowest) ]funded for 2003-4 and 2004-5 US LC Conference

  6. 12-bit Pipelined Digitizer 13 bit: round to 0 or 12 bit linput crudely digitized by 1st 3-bit cell ] digitized value subtracted from input ]difference is amplified by 8 and sent to 2nd 3-bit cell… US LC Conference

  7. Digitizer for Multi-bunch BPM lmost challenging digitizer: 11 bit, 2 G samples/s, 500 MHz bandwidth l input: sequence of doublets at 1.4 ns batch spacing ncharacterize with one parameter: pulse height nminimum sampling: 1/1.4 ns = 714 MHz ] interleaving 3 digitizers for redundancy ] 2 G samples/s US LC Conference

  8. Precision lsubmicron CMOS supply voltage: 2.5 V ] differential signal: ~ 1.6 V full swing ]LSB: 1.6 V/212 = 390 mV ]stability/accuracy of comparator thresholds, amplifier & S/H gains, charge injection: 195 mV = 0.5 LSB = 0.5/212 → 0.012% US LC Conference

  9. Fabrication Process lgain-bandwidth requirement: n assume 0.7 ns for sample and 0.7 ns for hold n settling to 0.5 LSB for 12-bit digitizer requires 9t: 0.5/212 ~ e-9 ]t = 0.7 ns/9 = 78 ps ]rise time = 2.2 t = 171 ps ]gain x bandwidth = 8 x 1/2pt = 16.4 GHz ]IBM process SiGe BiCMOS 6HP/6DM via MOSIS: ☺40 GHz NPN bipolar transistors US LC Conference

  10. 3-Bit Cell US LC Conference

  11. 3-Bit Cell Status ü ü ü ü ü ü ü ü ü ü ü ü ü ü lSimulate with Cadence sample/hold + flash ADC/flip-flop: designed/simulatedfrom schematic with parasitic capacitances multiplexer: logic is fast but somewhat noisy op-amp + encoder: use real devices in simulation ü ü ü US LC Conference

  12. Sample/Hold Status ldesign and simulated from schematic with parasitic capacitances switch-on resistance small enough to allow 9t in 700 ps switching offset (noise) largely cancelled with dummy switch: n100 mV ] 1 mV ü ü US LC Conference

  13. Cadence Simulation of Sample/Hold Progress Amplifier: ideal switch charge injection Amplifier: Jan. 04 design Amplifier: July 04 design US LC Conference

  14. Simulation of Amplifier AMP Specs rise time goal: 171 ps ] achieve:186 ps need DV=195mV for 12-bit precision January 2004 DV=298mV July 2004 DV=194mV US LC Conference

  15. Current S/H Simulation Issue Issues to be resolved: Offset from S/H not constant. Offset is a function of input signal slope. VT(“/vin”) ≡ input to 1st S/H VT(“/out2”) ≡ Output from 2nd S/H Offsets differ by ~2.8mV US LC Conference

  16. Plans lYear 2004-5: n complete design of amplifier + 3-bit cell n layout, submission, and testing of the building block circuits lYear 2005-7 n layout, submission, and testing of the prototype digitizer n radiation hardness tests n continued system design of prototype 11-bit digitizer US LC Conference

  17. EXTRA SLIDES FOLLOWS US LC Conference

  18. US LC Conference

More Related