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Design Methods and Circuit Techniques to Reduce Leakage in Deep Submicron

Design Methods and Circuit Techniques to Reduce Leakage in Deep Submicron. Christian Piguet, CSEM, Neuchâtel, Switzerland Stefan Cserveny, CSEM Jean-Félix Perotto, CSEM Jean-Marc Masgonty, CSEM. Leakage: Dramatic Situation.

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Design Methods and Circuit Techniques to Reduce Leakage in Deep Submicron

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  1. Design Methods and Circuit Techniques to Reduce Leakage in Deep Submicron Christian Piguet, CSEM, Neuchâtel, Switzerland Stefan Cserveny, CSEM Jean-Félix Perotto, CSEM Jean-Marc Masgonty, CSEM

  2. Leakage: Dramatic Situation • From 1992 to 2002, most of the work in power reduction has been performed for dynamic power • Today, for deep submicron, there is a clear shift: leakage or static power is a dramatic issue • Leakage during active mode, leakage during Idle or Sleep mode, leakage is more dramatic for very long idle mode • Ad Hoc networks C. Piguet :: 29.08.2014 :: Page 3

  3. Istatic(A) slow-slow typical fast-fast -10oC 2.1E-06 1.2E-05 7.0E-05 25 oC 1.7E-05 8.2E-05 3.9E-04 50 oC 6.1E-05 2.5E-04 1.1E-03 130 nanometers technology Circuit with 5 millions of MOS, 0.6 Volt: - 1 mA leakage is larger than the total specified current!!!!! C. Piguet :: 29.08.2014 :: Page 4

  4. Total Power with Vdd and VT Reduction Optimum at 50% dynamic and 50% static • Dynamic power is reduced with Vdd2 • Static Power is increased exponentially with lower VT • There is an optimum for a given Vdd • But it is dependent on the activity At constant clock frequency C. Piguet :: 29.08.2014 :: Page 5

  5. Leakage Reduction Techniques Techniques at Circuit, Gate and Architecture Levels • Portables devices, Ad-Hoc networks: very low activity • Leakage reduction factors of 100 are often required • Circuit: Several VT, Variable VT, Shut down • Gate: Stacked transistors, Input Vectors • Architecture: Very few innovative techniques (a low activity is far from the optimum, the goal could be less transistors but higher activity) C. Piguet :: 29.08.2014 :: Page 6

  6. Circuit Techniques I Several VT or MTCMOS • Deep Submicron Technologies provide low and high VT • Low VT on the critical path, high VT elsewhere • 10-20% of the gates are low VT (for industrial circuits) • Achieved reduction factor of about 10 • Factor 7 for a processor of Hitachi • But factor 100 for its clock tree C. Piguet :: 29.08.2014 :: Page 7

  7. Vdd=2 V. 2 V. active mode 4 V. idle mode VTp= -0.2 V. active mode VTp= -0.6 V. idle mode Bias 0 V. active mode -2 V. idle mode VTn= 0.2 V. active mode VTm= 0.6 V. idle mode Circuit Techniques II Variable VT or VTCMOS or SATS • Bias voltages on substrates • High VT in idle or low activity modes • Low VT for speed performances • Dynamic VT shift Problem • In deep submicron, the slope factor n is smaller and smaller • Larger bias voltages are required for smaller VT variations • SOI: the slope factor n is very close to 1 C. Piguet :: 29.08.2014 :: Page 8

  8. Vdd VT Circuit Technique III I DTMOS S • Proposed for SOI • Gate connected to MOS body • VT is high when the MOS is off • VT is low when the MOS is on Direct Reverse Vss Diode substrate to source: input current Weak Inversion Logic • MOS in weak inversion, very low Vdd • If Vdd smaller than VT, very slow • Limited VTCMOS in direct and reverse polarization C. Piguet :: 29.08.2014 :: Page 9

  9. Vss Vss Vss’ Vss’>Vss Vss Without switches Leakage switches low VT high VT Switch size circuit Circuit Techniques IV Shut down of the circuit (I) • Switches in supply wires • Circuit voltage drop • High VT for switches, low VT for the circuit • Circuit MOS: source voltage at Vss’ higher than Vss: VT shift • But the voltage drop could be large, flip-flops loose their data Large Switches: - small leakage reduction but large speed Small Switches: - the contrary C. Piguet :: 29.08.2014 :: Page 10

  10. Circuit with NMOS sources connected to Vss’ Vss’ Switch IC - ISW LIMITER for Vss’ MNS GS Vss Circuit Techniques V Shut down of the circuit (II) • Technique to keep the data • Circuit drop is limited • Various circuits available • Discharge of Vss’ if too high • Very good technique • Applied to SRAM C. Piguet :: 29.08.2014 :: Page 11

  11. Gate-Level Techniques Many techniques, but they do not achieve large leakage reduction • Just to list them: • Logic families when leakage is very different for N-ch and P-ch • N-MOS logic, or P-MOS logic, or precharge logic • Stacked transistors • A given input vector for a gate/circuit C. Piguet :: 29.08.2014 :: Page 12

  12. Architecture Techniques I Paradigm Shift • A low activity is detrimental for the ratio static over dynamic power • For a given logic function, various architectures • Is it possible for this logic function to reduce the number of transistors (less leakage) by using more intensively the transistors, i.e. by increasing the activity? • Are non-pipelined, pipelined, parallel, …, architectures better ? • Assuming that this logic function require 100 gate transitions, how to design this function with the minimal number of MOS? • If 10’000 MOS, a= 1%; if 1’000 MOS, 1/10 leakage, same dynamic power (100 transitions) but a=10% C. Piguet :: 29.08.2014 :: Page 13

  13. Gate 1 Gate 2 Gate 3 Gate 4 Gate 5 Reference period idle Td =0.5 time reference period Architecture Techniques II Efficiency • Better use of transitions • Efficiency  = Td /period = Td * f (period=1/f) • The number of gates in series or logical depth LD • With 20 gates in series, using fully the reference period, each gate will use 1/20 of this period, and being idle during 19/20 • So the efficiency  = 1/20 = 5% • Finally:  = 1/LD C. Piguet :: 29.08.2014 :: Page 14

  14. Architecture Techniques III Design parameters for designing an architecture • Used for comparing architectures for a given logic function: • Activity a= nb of switching gates / total nb of gates • Efficiency  = 1/LD or the logical depth = LD • The total number of gates N • Load capacitance C of a logic gate • IOFF leakage of a logic gate • ION dynamic power of a logic gate C. Piguet :: 29.08.2014 :: Page 15

  15. Architecture Techniques IV Dynamic, static and total Energy (power*delay product) • Circuit with N gates, in a given clock period: • Edyn = a * N * C * Vdd2 • Estat = (1/f ) * N * Vdd * I0FF • Assuming full use of the clock period: fmax is the product of  by fmax (1/delay) of a single gate, so fmax =  * ION/(C*Vdd) • By uisng this expression in Estat, one has : Estat = (1/( * ION)) * N * C * Vdd2 * I0FF • So Etot = (a + 1/ * I0FF/ION) * N * C * Vdd2 proportional to LD in critical path still to be reduced C. Piguet :: 29.08.2014 :: Page 16

  16. VT Vdd Frequency 500 mV 1.2 V 1 GHz 0 mV 120 mV 0.5 GHz 0 mV 200 mV 1 GHz 0 mV 400 mV 2 GHz Architecture Techniques V Optimum total power at 50% dynamic and 50% static • Considering Etot = (a + 1/ * I0FF/ION) * N * C * Vdd2 • 50%-50% implies a = LD * I0FF/ION • Or I0N/IOFF = LD/a = 1/(*a) • The ratio I0N/IOFF could be small, i.e. 100, if LD=10 and a=0.1 • I0N/IOFF = 100 implies VT close to 0 Volt in 0.13 m at 27C, If LD=100, a=0.01,  high VT and high Vdd C. Piguet :: 29.08.2014 :: Page 17

  17. VT Vdd Dynamic. Static Total 370 mV 1.5 33 mW 0 mW 33 mW 300 mV 1.25 25 mW 0 mW 25 mW 200 mV 0.97 15 mW 4 mW 19 mW 150 mV 0.83 10 mW 7 mW 17 mW 100 mV 0.7 8 mW 13 mW 21 mW 50 mV 0.55 7 mW 26 mW 33 mW Architecture Techniques VI Assuming same speed performances [mV] C. Piguet :: 29.08.2014 :: Page 18

  18. Architecture Techniques VII Design rules at the architecture level • To reduce drastically the total energy, one has to: • To reduce Vdd and VT (to have reasonable speed) • To have a low ratio I0N/IOFF , for instance 100 • 50% - 50% dynamic versus static, i.e. I0N/IOFF = LD/a • Logic depth LD and activity a are the design parameters • Architectures with small LD and high a C. Piguet :: 29.08.2014 :: Page 19

  19. Architecture Techniques VIII Design parameters LD and a • To reduce LD and increase a: • Small LD requires pipelining or very fast architectures • High activity is confusing, as many techniques for reducing activity have been proposed to reduce dynamic power • It is not a non-useful increase of activity, such as glitches • It has to be understood as reducing the total number of gates in the activity = nb switching gates / total nb gates, by keeping constant the number of switching gates (but activity depends also on modes) C. Piguet :: 29.08.2014 :: Page 20

  20. Architecture Techniques IX Pipelined architectures • To reduce LD • ¼ LD • Activity is the same • Registers are neglected • For the same throughput, i.e. same frequency for the two architectures, the same number of gates are switching. • I0N/IOFF = LD/a is 4 times smaller for the pipelined architecture C. Piguet :: 29.08.2014 :: Page 21

  21. Architecture Techniques X Parallel architectures • Does not reduce LD • Same activity • No effect • Other architecture? • Same number of transitions for a given logic function, but using less gates…. C. Piguet :: 29.08.2014 :: Page 22

  22. Conclusion Leakage: Very important and interesting problem • Has to be considered at circuit, gate and architecture levels • Circuit Level: Reduction factors of about 100 achievable • Gate Level. Only moderate reduction factors • Architecture Level: to be checked • Back to the old time ? • When designers have to reduce the number of MOS, to re-use the same units, serial architectures? C. Piguet :: 29.08.2014 :: Page 23

  23. T h a n k y o u f o r y o u r a t t e n t i o n.

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