332:578 Deep Submicron VLSI Design Lecture 6 Circuit Characterization of Resistance and Capacitance

1. 332:578 Deep SubmicronVLSI DesignLecture 6 Circuit Characterization of Resistance and Capacitance Michael L. Bushnell -- CAIP Center and WINLAB ECE Dept., Rutgers U., Piscataway, NJ Deep Submicron VLSI Des. Lec. 6

2. Outline • Simplistic Delay Model • Logical Effort Review • Resistance • Capacitance and Distributed RC Effects • Summary Material from: CMOS VLSI Design By Neil E. Weste and David Harris Deep Submicron VLSI Des. Lec. 6

3. Critical Paths • Slowest timing paths that limit a chip’s speed • Affect critical paths at these levels: • Architecture • RTL/Logic gate levels • Circuit level • Layout level • RTL/logic level – pipelining, gate types, fanin & fanouts • Circuit level – resize transistors to speed up • Layout level – speed up by changing physical layout • False paths – appear to be critical paths, but cannot propagate transitions due to Boolean value conflicts Deep Submicron VLSI Des. Lec. 6

4. Delay in a Logic Gate • Express delays in process-independent unit t = 3RC  12 ps in 180 nm process 40 ps in 0.6 mm process Deep Submicron VLSI Des. Lec. 6

5. Delay in a Logic Gate • Express delays in process-independent unit • Delay has two components Deep Submicron VLSI Des. Lec. 6

6. Delay in a Logic Gate • Express delays in process-independent unit • Delay has two components • Effort delayf = gh (a.k.a. stage effort) • Again has two components Deep Submicron VLSI Des. Lec. 6

7. Delay in a Logic Gate • Express delays in process-independent unit • Delay has two components • Effort delay f = gh (a.k.a. stage effort) • Again has two components • g: logical effort • Measures relative ability of gate to deliver current • g 1 for inverter Deep Submicron VLSI Des. Lec. 6

8. Delay in a Logic Gate • Express delays in process-independent unit • Delay has two components • Effort delay f = gh (a.k.a. stage effort) • Again has two components • h: electrical effort = Cout / Cin • Ratio of output to input capacitance • Sometimes called fanout Deep Submicron VLSI Des. Lec. 6

9. Delay in a Logic Gate • Express delays in process-independent unit • Delay has two components • Parasitic delay p • Represents delay of gate driving no load • Set by internal parasitic capacitance Deep Submicron VLSI Des. Lec. 6

10. Synopsys Model Deep Submicron VLSI Des. Lec. 6

11. Limitations of Linear Delay Model • Input/output slope • Input arrival times • Gate-source capacitance • Bootstrapping Deep Submicron VLSI Des. Lec. 6

12. Input/Output Slope • Largest error – as I/P rise time increases, delay increases – active transistor not turned all the way on at once • Delay vs. rise time is linear: Deep Submicron VLSI Des. Lec. 6

13. Slope Effect Deep Submicron VLSI Des. Lec. 6

14. Adjusted Synopsys Equations • 20 to 80% gate rise/fall time is 1 to 1.5x propagation delay • Input slope related to prior gate’s delay • Fast circuits have consistent slopes – slow ones may not Deep Submicron VLSI Des. Lec. 6

15. Gate-Source Capacitance • Needs to be charged/discharged during switching Deep Submicron VLSI Des. Lec. 6

16. Input Arrival Times • Erroneous to assume that one input of multi-input gate switches while others remain stable • 2 inputs to series transistor stack switch simultaneously • Delay longer than predicted • Both transistors only partially on, initially • 2 inputs to parallel transistor stack switch simultaneously • Delay shorter than predicted • Both transistors deliver current to output Deep Submicron VLSI Des. Lec. 6

17. Delay of FO3 2-Input NAND Deep Submicron VLSI Des. Lec. 6

18. Bootstrapping • Cgd delays inverter I/P and O/P waveforms • Sometimes Cgd multiplied by gain of gate – Miller effect • Happens when inverter biased in linear region near VDD/2 Deep Submicron VLSI Des. Lec. 6

19. Gate-Source Capacitance Deep Submicron VLSI Des. Lec. 6

20. More Limitations of Logical Effort • Neglects velocity saturation effects • Overestimates logical effort of NANDs • Does not account for interconnect • Accurate for high-speed data path and array circuits • Hard to analyze paths with complex branching • Explains how to design for maximum speed • Does not explain design for minimum area or low power given a fixed speed • Extract logical effort parameters directly from library data sheets Deep Submicron VLSI Des. Lec. 6

21. R of Non-Rectangular Shapes Deep Submicron VLSI Des. Lec. 6

22. R of Non-Rectangular Shapes Deep Submicron VLSI Des. Lec. 6

23. Formulae for Non-Rectangular Shapes Deep Submicron VLSI Des. Lec. 6

24. Capacitance Deep Submicron VLSI Des. Lec. 6

25. C Approximations • Field solver required to get accurate C • Approximate as sum of parallel plate C of width w = t/2 and cylindrical C with radius t/2 • Accurate within 10% when t  handaspect ratio < 2 Deep Submicron VLSI Des. Lec. 6

26. C Approximation Diagram Deep Submicron VLSI Des. Lec. 6

27. Efficient Approximation • Empirical formula – accurate and easy to compute • Good to 6% for aspect ratios < 3.3 • Failings of both formulae: • Do not consider layer interactions on same or higher layers • Conservative C for propagation delay and power estimation – assume that layers above and below are ground planes • Conservative C for contamination delay – assume no other layers Deep Submicron VLSI Des. Lec. 6

28. Wire Capacitance • Wire has capacitance per unit length • To neighbors • To layers above and below • Ctotal = Ctop + Cbot + 2Cadj Deep Submicron VLSI Des. Lec. 6

29. Wire Length Guide • r = resistance/unit length • c = capacitance/unit length • l = wire length • Want twire << tgate, so Deep Submicron VLSI Des. Lec. 6

30. Summary • Simplistic Delay Calculation • Limitations of Logical Effort • Resistance – important for correct delay calculation • Capacitance – critical for correct delay calculation • Distributed RC Effects – critical for all long wires Deep Submicron VLSI Des. Lec. 6