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Example of modular design: ALU

Example of modular design: ALU. ALU logic symbol:. ALU. Exercise: construct an ALU to perform the operations in this function table:. ALU. Subdivide ALU function or partition ALU into bit slices A bit slice: a module that can be replicated (arrayed) to generate a n-bit ALU. ALU.

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Example of modular design: ALU

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  1. Example of modular design: ALU • ALU logic symbol:

  2. ALU • Exercise: construct an ALU to perform the operations in this function table:

  3. ALU • Subdivide ALU function or partition ALU into bit slices • A bit slice: a module that can be replicated (arrayed) to generate a n-bit ALU

  4. ALU • Further partition the bit slice into a Logic Unit and an Arithmetic Unit

  5. ALU • Implement the logic unit module Truth table: Simple multiplexer realization

  6. ALU • K-map of the LU, and the minimized LU circuit:

  7. ALU • Implement the Arithmetic Unit • Block diagram of the AU slice

  8. ALU

  9. ALU

  10. ALU • Complete 1-bit slice

  11. Programmable logic devices • Goal: place as much functionality on a single chip as possible • Increases speed • Reduces power consumption, size, weight • IC design methodologies can be classified according to the level of design effort expended in obtaining the chip • Can range from full custom to none • Each has its advantages and drawbacks

  12. IC design methodologies • Full custom • Design every aspect of the chip – gate placements, routing, etc. • Complete control over all circuit parameters • Slowest to design and manufacture • Semi-custom • Use some pre-designed components, design the rest • None • Uses pre-fabricated SSI or LSI chips, just interconnect on PCB

  13. IC design methodologies • Semi-custom • Standard Cell libraries • Use pre-designed units, just place and interconnect • All processing steps need to be done (same as full custom) • Fabrication delay weeks or months • Pre-designed gate arrays • They are ICs containing unconnected gates • Only interconnection layer needs to be fabricated • Fabrication delay is days or weeks • PLDs • Gate arrays with flexible interconnections included • Fabrication delay is hours or days

  14. Programmable logic devices • PLA circuits • Built around homogeneous arrays of elementary components that can be configured to perform logical AND and OR operations • We look at basic structures that can realize AND, OR functions (in reality PLAs are based on NAND/NOR functions in CMOS technology) • PLAs can belong to • Gate arrays, if interconnect layer is not finished • PLDs, if fuses are provided along with a full interconnect layer • FPGA are PLD

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