Introduction to make

1. Introduction to make Nick Czebiniak Mark Santaniello March 23, 2001

2. Agenda • What is make • Why use make • Simple Example • Syntax • Macros • Suffixes • Further Information • Questions

3. What is make? • Make is a command generator • A tool for maintenance of a software development project • A way to manage dependency relations between files

4. Why use make • Automate and simplify compilation • To avoid unnecessarily rebuilding modules • To provide consistent cleanup and installation

5. Simple Example • Show a simple Makefile for three separate files main.c alpha.c beta.c gamma.s

6. Simple Example • By compiling the program manually, this needs to be done: cc –c main.c cc –c alpha.c cc –c beta.c as –o gamma.o gamma.s cc –o prog main.o alpha.o beta.o gamma.o

7. Simple Example • Using a Makefile: prog: main.o alpha.o beta.o gamma.o cc –o prog main.o alpha.o beta.o gamma.o main.o: main.c cc –c main.c alpha.o: alpha.c cc –c alpha.c beta.o: beta.c cc –c beta.c gamma.o: gamma.s as –o gamma.o gamma.s

8. Simple Example • To compile the program: make prog • This will compile the files and generate the executable program • On the command line, simply type: prog

9. Syntax • Tabs are required before a command line • #  comment line • \  continuation of a long line • RCS tags still can be used # $Id$ # $Log$ • Targets do not require prerequites clean: /bin/rm –f core *.o prog

10. Syntax • Can have multiple dependency lines file.o: file.c cc –c file.c # Command line file.o: global.h defs.h • Commands: • Cannot use aliases • Cannot use environment variables • Cannot use cd

11. Macros • They are of the form: name = text string • They are referenced by: ${name}

12. Macros Example LIBES = -lX11 Objs = draw.o plot_pts.o root_data.o CC = /usr/fred/bin/cc BINDIR = /usr/local/bin DEBUG_FLAG = # empty now, but assign –g for # debugging plot: ${Objs} ${CC} –o plot ${DEBUG_FLAG} ${Objs} ${LIBES} mv plot ${BINDIR}

13. Macros • Can use macros in macro definitions ABC = XYZ FILE = TEXT.${ABC} • If a macro is never defined, defaults to NULL • Order of macro definition is not important • A macro must be defined before any dependency that uses it

14. Macros • Internally predefined macros ${CC}  Always C compiler ${LD}  Always linker • Environment variables are macros • You can see all predefined macros by typing: make -p

15. Macros • Internal macros for prerequisites and targets $@  The current target $?  prerequisites newer than the current target • Example: libops: interact.o sched.o gen.o ar r $@ $?

16. Suffix • Can drastically reduce makefile size • Example: .SUFFIXES : .o .c .c.o: ${CC} ${CFLAGS} –c $< • $<  Evaluates to whatever prereq triggered the rule. • See the default suffix rules with make -p

17. Suffix • Simple makefile revisited OBJS = main.o alpha.o beta.o gamma.o prog: ${OBJS} ${CC} –o ${OBJS} • This is the entire make file

18. Notables • gmake vs. make • makemake • makedepend

19. Further Information • Managing projects with Make • man make • Web search on Makefile

20. QuestionsComments