PKUnity: A SoC Design and Verification Platform

PKUnity: A SoC Design and Verification Platform Lu Junlin MicroProcessor R&D Center (MPRC) Peking University

Outline • PKUnity SoC Platform Features • Multi-Layers Verification Framework • CDC Verification Tool • Future Works

What for • Providing a PLATFORMfor implementing and verifying NEW IDEALS in Nanotechnologies Low Power Softwares Behavioral Level Simulation (SystemC) Compiler Synthesis RTL Simulation/Emulation (Verilog/VHDL) New Ideas CPU FPGA Prototyping Silicon Proving Network On-chip communication PKUnity Platform Multi-Media Processing

What is • PKUnity Platform includes: • a scalable and configurable SoC architecture • a series of UniCore CPU • plenty of communication IPs • a verification framework • some verification tools • compilation tool chain and OS based on UniCore

PKUnity Architecture Low Speed I/O and System Modules UniCore CPU Memory and High Speed I/O

Design Features

Design Features • CPU • 600MHz UniCore • 8-Stage Pipeline • 64-bit Floating Point Co-Processor • 16KB I/D Cache • 2-Port Bus Interface • Main Memory • DDR (Double Data Rate) SDRAM • 166MHz Clock and 64-bit Width • 2 Memory Access Channels

Design Features • High Speed I/O Devices • 10M/100M/1G Ethernet MAC • 66MHz PCI Bridge • IDE SATA Controller • USB OTG Controller • Low Speed I/O Devices • UART • I2C • SPI • AC’97 • PS/2

Design Flow Design and Implementation RTL Simulation and Emulation SystemC-based HW/SW Co-verification FPGA Prototyping RTL Sign Off

Challenges • Gap between CPU and Main Memory • Different Bus Bandwidth Requirements • Power Supply Design & Verification • Complex Communication Protocol • Lots of Asynchronous Clock Domains

Design Solutions • Two-Layer bus • CPU-MEM bus • IO-MEM bus Fast Clock Best Performance CPU-MEM Bus Minimize CPU-MEM bandwidth gap Reduce the power supply Slow Clock Enough Performance IO-MEM Bus

Verification Solutions • Multi-Layer Verification Framework • For Complex Communication Protocol • CDC Verification Tool • For Lots of Asynchronous Clock Domains

Verification Challenges • Complex Communication Protocol • AHB vs. DDR SDRAM • AHB vs. PCI • AHB vs. MAC • AHB vs. USB OTG • AHB vs. IDE • APB vs. AC’97 • … It’s hard to cover all the transaction types!

Verification Methodology • Multi-Layer • Signal Layer • Bus Layer • Transaction Layer • Scenario Layer

Self Checking • Self Checking by two channels

Verification Framework

Example • Ethernet MAC Verification Coverage

What’s CDC • CDC: Clock Domain Crossing

Challenges • Lots of Asynchronous Clock Domains • The relationship of clocks is static in the normal simulation • It’s difficult to find setup time and hold time violation (metastable state)

Method (Step 1) 1. Find all the CDC paths • Handshake Logic • Gray code counter • ...

Method (Step 2) 2. Insert a module which can provide random delays on each CDC paths CDC_delay U_RdDMA_D (.in(RdDMAH), .out(RdDMAH_d)); CDC_delay U_WrDMA_D (.in(WrDMAH), .out(WrDMAH_d)); Clk_jitter U_ICLK(.in(ICLK), .out(ICLK_j)); CDC_monitor U_RdDMA_M (.in(RdDMAH_d)); CDC_monitor U_WrDMA_M (.in(WrDMAH_d)); always @ (posedge HCLK) begin RdDMAH <= (RWCON & !RdDMAH); WrDMAH <= (!RWCON & !WrDMAH); end assign XCS <= !WrDMAH_d & !RdDMAH_d & CS0; always @ (posedge ICLK_j) NCS <= (WrReqI | RdReqI) & XCS;

Method (Step 3) It’s hard to reach 100% coverage, but it does find some severe bugs missed in the normal simulation! 3. Add reasonable delays on the CDC paths in simulation repeatedly

Example • A commercial ATA-5 IDE controller IP • The table shows coverage comparability after 30 transactions finished • The right diagram show the full coverage growth

Future Works • Communication Architecture • Bandwidth Allocation Algorithm • CDC Coverage Improvement • …

Thank You!

PKUnity: A SoC Design and Verification Platform