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SOC Final Project

Modification of AHB decoder circuit's address ranges and operation logic for improved functionality and performance.

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SOC Final Project

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  1. SOC Final Project 第四組 R91921042 蘇倉弘 R91921054 莊銘罡 R90921003 陳健志

  2. SOC Final Project AHBDecoder更改部份: • assign iHSELMYIP = ((iHSELLOGICMODULE == 1'b1) & (HADDR[27:7] == 21'b110000000000000000000)) ? 1'b1 : 1'b0; 更改成 • assign iHSELMYIP = ((iHSELLOGICMODULE == 1'b1) & (HADDR[27:8] == 20'b11000000000000000000)) ? 1'b1 : 1'b0; LM_MYIP registers address range : 0xCC000000~0xCC0000FF

  3. SOC Final Project • assign iHSELDefault = ((iHSELLOGICMODULE == 1'b1) & • ~(HADDR[27:25] == 3'b000) & • ~(HADDR[27:20] == 8'b00100000)& • ~(HADDR[27:7] == 21'b110000000000000000000)) ? 1'b1 : 1'b0; 更改成 • assign iHSELDefault = ((iHSELLOGICMODULE == 1'b1) & • ~(HADDR[27:25] == 3'b000) & • ~(HADDR[27:20] == 8'b00100000)& • ~(HADDR[27:8] == 20'b11000000000000000000)) ? 1'b1 : 1'b0;

  4. myIP部分更改部份 `ST_READ : if (Valid == 1'b1)begin case(HADDR[6:0]) 7'b0100000: i_out<=out0; 7'b0100100: i_out<=out1; 7'b0101000: i_out<=out2; 7'b0101100: i_out<=out3; 7'b0110000: i_out<=out4; 7'b0110100: i_out<=out5; 7'b0111000: i_out<=out6; 7'b0111100: i_out<=out7; 7'b1000100: i_out<=rr; endcase 更改成 `ST_READ : if (Valid == 1'b1)begin case(HADDR[7:0]) 8'b10000000: i_out<=out0; (0xCC000080) 8'b10000100: i_out<=out1; (0xCC000084) 8'b10001000: i_out<=out2; (0xCC000088) 8'b10001100: i_out<=out3; (0xCC00008C) 8'b10010000: i_out<=out4; (0xCC000090) 8'b10010100: i_out<=out5; (0xCC000094) 8'b10011000: i_out<=out6; (0xCC000098) 8'b10011100: i_out<=out7; (0xCC00009C) 8'b10100000: i_out<=rr; (0xCC0000A0) endcase SOC Final Project

  5. 原始程式 `ST_WRITE : if (Valid == 1'b1)begin case(HADDR[6:0]) 7'b0000000: i_in0<=HWDATA[31:0]; 7'b0000100: i_in1<=HWDATA[31:0]; 7'b0001000: i_in2<=HWDATA[31:0]; 7'b0001100: i_in3<=HWDATA[31:0]; 7'b0010000: i_in4<=HWDATA[31:0]; 7'b0010100: i_in5<=HWDATA[31:0]; 7'b0011000: i_in6<=HWDATA[31:0]; 7'b0011100: i_in7<=HWDATA[31:0]; 7'b1000000: enable<=HWDATA[31:0]; endcase 更改為 `ST_WRITE : if (Valid == 1'b1)begin case(HADDR[7:0]) 8'b11000000: i_in0<=HWDATA[31:0]; (0xCC0000C0) 8'b11000100: i_in1<=HWDATA[31:0]; (0xCC0000C4) 8'b11001000: i_in2<=HWDATA[31:0]; (0xCC0000C8) 8'b11001100: i_in3<=HWDATA[31:0]; (0xCC0000CC) 8'b11010000: i_in4<=HWDATA[31:0]; (0xCC0000D0) 8'b11010100: i_in5<=HWDATA[31:0]; (0xCC0000D4) 8'b11011000: i_in6<=HWDATA[31:0]; (0xCC0000D8) 8'b11011100: i_in7<=HWDATA[31:0]; (0xCC0000DC) 8'b11100000 : enable<=HWDATA[31:0]; (0xCC0000E0) endcase SOC Final Project

  6. SOC Final Project 原始程式 if(enable == 31‘d0) begin j <= 31'd0; rr <= 31'd0; end elseif(enable==31'd1) if(k==31'd1) begin begin x0[10:0] <= in0[10:0]; x1[10:0] <= in1[10:0]; x2[10:0] <= in2[10:0]; x3[10:0] <= in3[10:0]; x4[10:0] <= in4[10:0]; x5[10:0] <= in5[10:0]; x6[10:0] <= in6[10:0]; x7[10:0] <= in7[10:0]; x0[11]<= in0[31]; x1[11]<= in1[31]; x2[11]<= in2[31]; x3[11]<= in3[31]; x4[11]<= in4[31]; x5[11]<= in5[31]; x6[11]<= in6[31]; x7[11]<= in7[31]; end if(k==31'd5) begin out0 <= y0; out1 <= y1; out2 <= y2; out3 <= y3; out4 <= y4; out5 <= y5; out6 <= y6; out7 <= y7; rr <= 31'd1; end

  7. SOC Final Project 更改為 always @(enable) begin case(enable) 32'h00000002: begin x0[10:0] <= in0[10:0]; x1[10:0] <= in1[10:0]; x2[10:0] <= in2[10:0]; x3[10:0] <= in3[10:0]; x4[10:0] <= in4[10:0]; x5[10:0] <= in5[10:0]; x6[10:0] <= in6[10:0]; x7[10:0] <= in7[10:0]; x0[11]<= in0[31]; x1[11]<= in1[31]; x2[11]<= in2[31]; x3[11]<= in3[31]; x4[11]<= in4[31]; x5[11]<= in5[31]; x6[11]<= in6[31]; x7[11]<= in7[31]; end 32'h00000004: begin out0 <= y0; out1 <= y1; out2 <= y2; out3 <= y3; out4 <= y4; out5 <= y5; out6 <= y6; out7 <= y7; rr <= 31'd1; end

  8. SOC Final Project Driver.h檔更改前的設定 #define LM_MYIP 0xCC000040 更改後的設定 #define LM_MYIP 0xCC000080

  9. SOC Final Project Driver.cpp檔更改前的程式: int *ptr; ptr=(int *)0xcc000040; *ptr=0; int *write_head; write_head=(int *)0xcc0000C0; *write_head=*x0; *(write_head+1)=*x1; *(write_head+2)=*x2; *(write_head+3)=*x3; *(write_head+4)=*x4; *(write_head+5)=*x5; *(write_head+6)=*x6; *(write_head+7)=*x7; *ptr=1; pooling(); int *read_head; read_head=(int *)0xcc000020; *x0=*read_head; *x1=*(read_head+1); *x2=*(read_head+2); *x3=*(read_head+3); *x4=*(read_head+4); *x5=*(read_head+5); *x6=*(read_head+6); *x7=*(read_head+7);

  10. SOC Final Project 更改後的程式 int *ptr; ptr=(int *)0xcc0000E0; *ptr=2; int *write_head; write_head=(int *)0xcc0000C0; *write_head=*x0; *(write_head+1)=*x1; *(write_head+2)=*x2; *(write_head+3)=*x3; *(write_head+4)=*x4; *(write_head+5)=*x5; *(write_head+6)=*x6; *(write_head+7)=*x7; pooling(); *ptr=4; int *read_head; read_head=(int *)0xcc000080; *x0=*read_head; *x1=*(read_head+1); *x2=*(read_head+2); *x3=*(read_head+3); *x4=*(read_head+4); *x5=*(read_head+5); *x6=*(read_head+6); *x7=*(read_head+7);

  11. SOC Final Project 2-D DCT MATRIX 2-D IDCT MATRIX

  12. Original Picture SOC Final Project

  13. SOC Final Project (Software-DCT)

  14. SOC Final Project (Hardware-DCT)

  15. SOC Final Project • Benchmark Replace software DCT encoder by hardware DCT encoder

  16. SOC Final Project • Future Work • Add RGB->YUV, and Quantizerencoder to MYIP

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