July ITRS IRC Plenary inputs Incl. Three Scaling-Related Definitions Proposal, Rev 3 - 07/10/06

1. Assessment of the potential value return from research topicsFollow-up IRC actions from ITRS Maastricht, 04/07/06 July ITRS IRC Plenary inputs Incl. Three Scaling-Related Definitions Proposal, Rev 3 - 07/10/06

2. Food for thought from the IRC • “Moore’s Law and its continuance is an economic rather than a technical statement” (Bernard Meyerson, chief technologist for IBM’s Systems & Technology Group). • “Clock frequency is not the [only] driver of system performance. You can get a better result by making tradeoffs to balance numerous aspects of performance” (adapted from Bernard Meyerson) • Classical Scaling -- the glue that connects Moore’s Law to performance – is enhanced by “equivalent scaling”. • There are additional ways to enhance economic and technical performance in conjunction with, or without, scaling.

3. More than Moore: Diversification 130nm 90nm 65nm More Moore: Miniaturization 45nm 32nm 22nm . . . V Pursuing the race for added value for the end customer bycombining on-chip ULSI and off-chip integration Analog/RF Passives HV Power Sensors Actuators Biochips Interacting with people and environment Non-digital content System-in-package (SiP) [Geometrical + Equivalent Scaling] Baseline CMOS: CPU, Memory, Logic Information Processing Digital content System-on-chip (SoC) Combining SoC and SiP: Higher Value Systems 2005 edition Beyond CMOS

4. Three Scaling-Related Definitions Glossary Proposal • In order to clarify the IRC/TWG work on innovation and value, below is a proposal for three scaling-related definitions to be added to the Executive Summary Glossary in the 2006 Update: • Geometrical (constant field) Scaling (“More Moore”) refers to the continued shrinking of horizontal and vertical physical feature sizes of the on-chip logic and memory storage functions in order to improve density (cost per function reduction) and performance (speed, power) and reliability values to the applications and end customers. Examples (not exhaustive) are: a) horizontal half-pitch feature size (f^2) for density/cost; b) gate insulator thickness for speed and power performance; c) gate length for speed performance. Slowing of geometrical scaling reduces the rate at which the end applications and customers receive value benefits, requiring new “equivalent scaling” material and/or gate enhancements. • 1+) Equivalent Scalingwhich occurs in conjunction with, and also enables, continued Geometrical Scaling, refers to 3-dimensional device structure (“Design Factor”) Improvements plus other non-geometrical process techniques and new materials that affect the electrical performance of the chip. Examples (not exhaustive) are: a) horizontal or vertical function design factor (i.e. 3-dimensional capacitor and transistor designs); b) strained silicon in the transistor gate; c) flash memory electrical multi-bit-cell; d) high-K capacitor material for enhanced DRAM storage effectiveness; e) high-K transistor gate material substitutes for insulator thickness scaling; f) low-K chip-level interconnect material. Electrical equivalent scaling can enhance the value benefits of geometrical scaling.

5. Three Scaling-Related Definitions Glossary Proposal [Definitions continued] 2) “More than Moore” refers to System-on-Chip (SOC) and/or System-in-Package (SIP) techniques and materials that provide additional chip, board, and system-level cost and performance value to the application and end customer, in conjunction with geometrical and equivalent scaling. Examples (not exhaustive) are: a) Large cache memory management architecture; b) Multi-core MPU architecture; c) on-chip logic plus software power management; d) stacked chips with through-vias for board-level density and power; e) Packaging low-K interconnect materials; and f) diverse Specialized Functionality such as AMS/RF, Image Sensors, Sensors/Actuators (including MEMS), Embedded Passives, etc.

6. Three Scaling-Related Definitions Glossary Proposal and Examples Outline (including value to application/customer) • “More Moore” (MM) - Geometrical (constant field) scaling • Horizontal – half-pitch feature size (f2) (Moore’s Law, Function Size, Density) • Vertical – Gate Insulator Thickness (limit of Silicon Oxide) (Performance – speed, power) • Horizontal – Gate Length (Performance – speed, power) (1+).Equivalent scaling - Device Design and Process Techniques a) Vertical function design factor for density/cost, i.e. 3-D capacitor and transistor designs (Density/cost, Performance – speed, power) b) Strained Silicon (enhances gate current performance without gate insulator thickness reduction, while horizontal gate length continues to scale) MPU/ASIC (Performance – speed, power) c) Flash bit multi-cell (Density/cost) - Materials d) High K Capacitor DRAM (Performance – Storage Effectiveness/Reliability) e) High K Gate MPU/ASIC (enhances gate performance without vertical scaling, while horizontal gate length continues to scale) (Performance – speed, power) f) Low K Interconnect (Performance – speed, power) 2. ‘More Than Moore” (MtM) – Additional SOC and/or SIP , in conjunction with, or without, Geometrical and Equivalent chip scaling (chip, package, board, and system-level density/cost, performance - speed and power) • Large Cache • Multi-core • On-chip logic plus software power management • Stacked Chips with through-vias • Package Low-K Interconnect Material • Specialized Functionality • AMS/RF • Image Sensors • Sensors/Actuators (including MEMS) • Embedded Passives • Etc.

7. Follow-up process • Start working now on the subject of “equivalent scaling parameters” • Topic to be included in the TWG meetings • Conference call early June • Joint conf call with IRC / some TWG chairs • Summer meeting • Half-day workshop IRC / selected TWG chairs • Contact with other consortia • MEMS Industry group (A.Allan) • iNEMI (A.Allan, JA.Carballo) • IEEE (P.Gargini)

8. To be discussed in the TWG meetings • Former approach • Economic value through dimensional scaling • Proposed Approach • It is appropriate to evaluate the benefit of the addition of beyond Moore with respect to the customer. • The IRC wants the TWGs to think “out of the box” and look beyond geometrical (constant field) and equivalent scaling

9. Possible topics that may interact with the economic value issue. • Working groups will continue to give input throughout 2006 for 2007 ITRS • What are other drivers? • How do we bring additional value to the customer - multi-dimensional and may need to think how best to guide research. • Questions for the CrossTWG meeting with the five teams [Interconnect, Design, PIDS, Wireless and A&P] TWG – • What value/benefit will pure continuing geometrical (constant field) and equivalent scaling bring ? • Which non-scaling (“More than Moore”) parameters will bring scaling-like value, such as: • meeting system performance/cost, or • bringing additional functionalities? • How to characterize / evaluate non-scaling parameters (of 2.) versus the continuing scaling approach? • Are there trade-offs involved between scaling and non-scaling parameters (e.g., frequency vs. # of multi-core processors)? • Is a cost-to-value tool needed to help evaluate trade-offs? What are the appropriate inputs/outputs for such a cost model? • The generic ITRS pre-competitive boundary timing is set by scaling and should be two technology generations (0.7x) from current technology level – • What is the pre-competitive boundary for the potential solution topic? • What is the necessary “critical mass” of interested companies?

10. Possible TWG involvement preparation/proposals for July ITRS • Assy & Packaging • System integration white paper • Passive integration • Design • Extension of roadmap / system drivers (example Automotive HV power, Sensors) • System on Chip / network on Chip • PIDS / Design • extending MASTAR to system level • Interconnect • Optical • Passive integration • RF Wireless • Passive integration • …

11. Format proposal Don’t feel restricted by that format ! Thinking out of the box is welcome !

12. Citation • P. Cogez “More Moore” and “More than Moore” Illustrations

13. Illustration: Geometrical Scaling (Constant Electric Field) Source: STM, ITRS IRC meeting – ca. July, 2006

14. Citation, slide 13 • “Is there still plenty of room at the bottom?” • Claude Weisbuch, LMC Polytechnic, and Michel Brillouet, CEA/LETI, Grenoble

15. 13.5 nm $100,000,000 193 nm ~ 50 $ M $10,000,000 Stepper Capital Cost $1,000,000 $100,000 1975 1980 1985 1990 1995 2000 2005 2010 2015 Year Illustration: Geometrical Scaling (Litho Cost Issues) Litho cost trend Source: STM, ITRS IRC meeting – ca. July, 2006

16. New DG SON – among best results ever reported Moore’s Laws can be prolonged beyond 22nm ! But ……..… -> Illustration: Geometrical Plus Equivalent Scaling Improvements of CMOS structure to cope with challenges Source: STM, ITRS IRC meeting – ca. July, 2006

17. TaO TaO Hf(Si)O SOP SOP AlO SiOC SiOC Porous SiOC Ta/TaN Ta/TaN Ta/TaN Cu Cu Cu SOI SiOF Note the Scale Change SiOF SiOF 2010 Str. Si SiGe SiGe SiGe TiSi TiSi NiSi CoSi W W W W Si(O)N Si(O)N Si(O)N Si(O)N Si(O)N Ti/TiN Ti/TiN Ti/TiN Ti/TiN TiW W, WSi W, WSi W,WSi WSi, PtSi WSi, MoSi (B)PSG (B)PSG (B)PSG (B)PSG (B)PSG (B)PSG AlCu Al-Cu Al-Cu Al-Cu Al-Si-Cu Al-Si Al SiO,,N SiO, N SiO, N SiO, N SiO, SiN SiO, SiN SiO, SiN Si,epi Si,epi Si,Epi Si,Epi Si,Epi Si,Epi Si …and more coming in 2010… 1960 1970 1980 1995 2000 2005 1990 Illustration: Equivalent Scaling (Cumulative Material Cost Issues) New Materials BEOL FEOL Starting Material Year From E. Kamerbeek, ASM Source: STM, ITRS IRC meeting – ca. July, 2006

18. R&D ~1 B$ R&D costs by generation 250nm 180nm 130nm 90nm Smaller Chips, Higher Entry Costs Illustration: Equivalent Scaling (Cumulative R&D Cost Issues) 2-4 B$ 0.1µ -> 0.032µ Production 300 mm At each step, production capacity doubles and critical dimensions halve 1-2 B$ 0.5µ -> 0.13µ Illustration: Scaling (Fab Cost Issues) 200 mm Illustration: Scaling (Technology R&D Cost Issues) Surface proportional to cost 100-200 M$ 5µ-> 0.8µ 70 M$ 20µ-> 5µ 150 mm 100 mm 1980 1985 1990 1995 2000 2005 Source: STM, ITRS IRC meeting – ca. July, 2006

19. iNEMI Vision of the Evolution of SiP(International Electronics Manufacturing Initiative) Illustration: Scaling plus “More than Moore” Source: Professor Rao Tummala, Georgia Institute of Technology-Packaging Research Center. Source: STM, ITRS IRC meeting – ca. July, 2006

20. Differentiation challengesHow to predict future applications? Projection done in 1954of home computer in 2004 Source: STM, ITRS IRC meeting – ca. July, 2006

21. Maybe turn to cartoonists ? Illustration of Moore’s original article (1965)

22. Backup

23. CMOS baseline memory RF HV Power passives sensors actuators bio, fluidics 1000 500 Moore’s Law 250 130 65 32 Non-CMOS devices, multi-chip, SiP solutions Technology Evolution 2000 2005 2010 2015 2020 size [nm]

24. Past Geometrical Scaling (G)  Moore’s Law Future Equivalent Scaling (E)  “More” Moore + Functional Diversification  More than Moore (MtM) (digital) (non-digital)

25. 1/2 P  G 1/2 E +MtM P  + New P ≠ 1/2

26. .7  V .7 ~.7 H P ~17% ~17% -50% -30—50% C - Transistor - Interconnect - Capacitor G E