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IRC Roll-Out/Plenary 4/4

IRC Roll-Out/Plenary 4/4. Technology “Node” identified by xx90 Minimum Half-Pitch of Metal 1 of either DRAM or Logic Logic “node” presently being represented by: (M1 Half-Pitch + Printed Gate Length)/2

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IRC Roll-Out/Plenary 4/4

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  1. IRC Roll-Out/Plenary 4/4 • Technology “Node” identified by xx90 • Minimum Half-Pitch of Metal 1 of either DRAM or Logic • Logic “node” presently being represented by: (M1 Half-Pitch + Printed Gate Length)/2 • System Drivers in National Electronic Manufacturers Initiative (NEMI) Roadmap will be reviewed in July Meeting • 2003 Executive Summary Outline will Include Wireless • Leave Current 3-year Columns of 2001 ITRS in 2003 ITRS Long-Term Columns for Reader Convenience • 2yr Basis for Long Term Years will be discussed by IRC for 2005 ITRS

  2. Yoshimi-san Proposal: 1. Define the technology node by the minimum half-pitch of metal-1, either in DRAM or MPU. 2. Add a header before the node number to distinguish from the non-ITRS nomenclature. As a header, use “half-pitch” (hp, 1/2p, HP) ex. “hp90nm technology”, “1/2p-65nm technology”, etc.

  3. Table Data from Yoshimi Proposal : • Directly measurable, technologically unambiguous. • Can smoothly trace the possible crossover of HP from DRAM to MPU. • Can be independent of non-ITRS convention. • Consistent with ITRS2001. Quite a minor alteration. • ITRS can stay ITRS.

  4. One Possible Solution: Stay Technology Node Unchanged but To Define and Describe the Logic Half Pitch (=Pitch/2) as M1 in the 2003 ITRS • Metal pitch • =Cell Pitch • (3) Poly Pitch • (2)Contacted • Metal 1 (M1) pitch Logic MPU/ASIC DRAM

  5. M1 Half-Pitch Could be Defined. But, What is Defined as Common Process Technology? ITRS DRAM HPRoadmap Seems Stabilized. Logic Technology Generation ( NOT Defined by ITRS) Seems Starting to Precede DRAM HP? 1000 Logic 180nm Tech. M1 Half Pitch 230 nm 1999 Logic 130nm Tech. M1 Half Pitch 180-165 nm 2001 Logic 250nm Tech. M1 Half Pitch 320 nm 1999 Logic 90nm Tech. M1 Half Pitch 120-110 nm 2003 Common Process Technology 90nm: ArF w PS, CD= (130nm: ArF,CD= ) (180nm: KrF w. PS CD= ) 1997 2001 DRAM ½ Pitch 1999 2001 MPU/ASIC ½ Pitch 2001 Technology Node - DRAM Half-Pitch (nm) 1999 ITRS DRAM 100 DRAM HP 90nm (130nm) (180nm) Logic M1 HP 120nm (180nm) (230nm) Half-Pitch 2004 250 320 0.78 180 230 0.78 130 180-165 0.72-0.79 90 120-110 0.75-0.81 TN M1 HP TN/M1HP 3-year Node Cycle 10 1995 1998 2001 2004 2007 2010 2013 2016 Year of Production Source: 2001 ITRS - Exec. Summary, ORTC

  6. M1 Half-Pitch Correlated to Physical Gate Length ITRS Roadmap Acceleration Continues…Gate Length 2002 ITRS Update – (No Changes from 2001 ITRS) 1000 M1 Half Pitch DRAM “1/2-Pitch” Node 2001 ITRS 2003 ITRS 2001 MPU Printed Gate Length 2001 MPU Physical Gate Length Technology Node - DRAM Half-Pitch (nm) 100 1999 ITRS MPU Gate-Length Taiwan Proposal: EUV @ 32nm =2013 in 2001 ITRS; =2012 in 2003 ITRS; =2009 on Logic 2-yr “Node” cycle 2-year Cycle 3-year Cycle 10 1995 1998 2001 2004 2007 2010 2013 2016 Year of Production Source: 2001 ITRS - Exec. Summary, ORTC “N90nm Node” “N65nm Node”

  7. Backup

  8. 2003 Outline • Foreword – P.Gargini • Introduction – TSIA/B.Doering • Overview • Technology Requirements • Potential Solutions • Wireless Technology - ESIA • Overall Roadmap Process and Structure – A. Allan • Technology Characteristics/Requirements Tables • Technology Nodes [Targets?] • Drivers for ITWG Technology Requirements

  9. 2003 Outline • Grand Challenges – Yoshimi-san/A.Allan • Overview • In the Near Term (through 2009) • Enhancing Performance • Cost-effective Manufacturing • In the Long Term (2010-2018) • Enhancing Performance • Cost-effective Manufacturing • Difficult Challenges – ITWG Chair Summary • Tables are contributed by ITWGs

  10. 2003 Outline • Overall Roadmap Technology – A.Allan Characteristics • Background • Overview of 2003 Revisions • Definitions • Roadmap Timeline • Product Generations and Chip-size Model • Trends [chip size, lithographic field, wafer size, etc.] • Performance of Packaged Chips • Electrical Defect Density • Power Supply and Dissipation • Cost

  11. 2003 Outline • Glossary – K or J - SIA/A.Allan • Characteristics of Major Markets • Chip and package—physical and electrical attributes • Fabrication attributes and methods • Maximum substrate diameter • Electrical design and test metrics • Design and test

  12. 2003 Outline • Technology Working Group Reports - ITWGs • System Drivers • Design • Test and Test Equipment • Process Integration, Devices and Structures • Emerging Research Devices • Front-end Processes • Lithography • Interconnect • Factory Integration • Assembly and Packaging • Environment, Safety and Health • Yield Enhancement • Metrology • Modeling and Simulation • Other?

  13. 2003 Outline • ITWG Reports Required Contents - ITWGs • Scope • Difficult Challenges • Technology Requirements • Potential Solutions • Cross-cut ITWG Issues • Inter Focus ITWG Discussion

  14. 2003 Citations • Cited Works / Footnoted Materials – ITWGs/L.Wilson • ITWG submits copies of cited works information • title page showing all authors • publisher, • Vol. No., • date published, • location published, • pages used • ITWG submits permission for use

  15. 2003 Table Templates • Difficult Challenges Tables • 5 challenges ³ 45nm / Through 2009 • 5 challenges <45nm / Beyond 2009 • Technology Requirements Tables • Proposed Near-term Year Header for All Tables • Proposed Long-term Year Header for All Tables

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