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Sync Distribution System with Clock and Switch Segments

Explore a detailed sync distribution system with clock and switch segments for efficient data distribution and management. Understand the architecture and functions of each segment. Last updated on 20/12/2006.

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Sync Distribution System with Clock and Switch Segments

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  1. ATCA LLP CARRIER BLOCK DIAGRAMS LAST UPDATE 20/12/2006 ISOCRATE R.

  2. 200Mhz Clock and SYNC distribution MASTER 200MHz SYNC SWITCH GTS GTS_CLOCK SYNC_RTN CLOCK_ SYNC FANOUT VIRTEX4 LX25 DATA DISTRIBUTON CORE SWITCH PLL CLOCK_ SYNC SWITCH SEGMENT 200MHz SMB INSP VIRTEX4 FX100 MAIN FPGA SEGMENT MGT CLOCK SYSTEM SLAVE 200MHz SYNC SWITCH SEGMENT GTS_CLOCK SYNC_RTN CLOCK_ SYNC FANOUT VIRTEX4 LX25 DATA DISTRIBUTON SEGMENT SWITCH PLL CLOCK_ SYNC SWITCH SEGMENT 200MHz SMB INSP VIRTEX4 FX100 MAIN FPGA SEGMENT TCLK MGT CLOCK SYSTEM

  3. Bcast & Msg Handler 1/2 FROM REMOTE (TCLK) 8 B_cast_data (7 downto 0) B_cast_str0 FANOUT TO MAIN FPGA, LOCALS MEZZANINES, AND REMOTE MEZZANINES (TCLK) SERIALIZERS 81 8 B_cast_str1 TRG/BCT FPGA 8 GTS Status (7 downto 0) GTS MEZZANINE MAIN FPGA LLP Status (7 downto 0) Msg_data (7 downto 0) Msg_str0 Msg_str1 FROM REMOTE (TCLK) Concentrator SEG/CORE MEZZANINE 8 LLP Status (7 downto 0) SERIALIZERS 81 TO REMOTE (TCLK) 8 Msg_data (7 downto 0) Msg_str0 8 Msg_str1

  4. Bcast & Msg Handler 1/2 TCLK PORT GTS Serializers FPGA CORE SEGMENT MAIN FPGA SEGMENT TCLK PORT SEGMENT Serializers FPGA SEGMENT SEGMENT MAIN FPGA SEGMENT

  5. TRIGGER Handler (serial) ?? (1 downto 0) Trig_val (1 downto 0) 8 Trig_Rej (1 downto 0) FANOUT TO OTHERS DEST Lt_data (7 downto 0) 8 SERs / DESERs 81 Lt_Strobe 8 GTS MEZZANINE Tv_data (7 downto 0) Tv_Strobe Trig_req (1 downto 0) MAIN FPGA Trig_req (1 downto 0) CORE MEZZANINE

  6. 44 lines TRIGGER & BCAST Handler (parallel) Trig_req (1 downto 0) Alignement BUS (3 lines) Trig_req (1 downto 0) 10pairs (20 lines) Trig_val (1 downto 0) 8 Trig_Rej (1 downto 0) 4 lines Lt_data (7 downto 0) 8 SERs / DESERs 81 Lt_Strobe 8 Sync_rtn Tv_data (7 downto 0) CORE MEZZANINE Sync SERs / DESERs 81 8 Tv_Strobe GTS MEZZANINE TCLK 8 B_cast_data (7 downto 0) B_cast_str0 B_cast_str1 8 GTS Status (7 downto 0) 8 8 8 8 200 lines 266 / 448 ~50% of LX25_FF668 44 lines 44 lines 44 lines 44 lines 44 lines CMC #1 CMC #2 CMC #3 CMC #4 FX100

  7. TRIGGER Handler 2/2 TCLK PORT GTS Serializers FPGA CORE SEGMENT MAIN FPGA SEGMENT TCLK PORT SEGMENT Serializers FPGA SEGMENT SEGMENT MAIN FPGA SEGMENT

  8. Data readout engine Using 1 16 bit port : 128 words/event 256 bytes/event 6 channels  1536bytes 16bit bus @ 100MHz Need 7.68µs (20µs avaible @ 50KHz) 1536*4 = 6144 byte/Event 32bit bus @ 100MHz Need 15.36µs (20µs avaible @ 50KHz) 8 pairs ; 16 I/O Serializer Data_A (15 downto 0) Deserializer Serializer Serializer Empty_A Serializer 32bit Data_Ready_A 32bit 1024x18 DPRAM Data_Request_A Data_A (15 downto 0) 9bit 9bit Empty_A Data_Ready_A Data_Request_A 1024x18 DPRAM X4 Mezzanines

  9. MGT Clocking Layout RocketIO 101 A B MUX RTM PCI EXPRESS LANE1 MGTclk M34/N34 RTM PCI EXPRESS LANE0 RocketIO 102 200MHz GTS Clock MUX A B USER SFP TRANSCEIVER MGTclk AP28/AP29 RocketIO 103 MUX A B PHASE LOCKED ATCA FABRIC CH11-CH12 RocketIO 105 100MHz GTS Clock A B MUX ATCA FABRIC CH9-CH10 INSPECTION PADS ATCA FABRIC CH7-CH8 RocketIO 106 LOCAL 100MHz (EPSON) A B MUX ATCA FABRIC CH5-CH6 ATCA FABRIC CH1-CH2 RocketIO 109 A B MUX ATCA FABRIC CH3-CH4 MGTclk AP3/AP4 RocketIO 110 A B MUX RTM PCI EXPRESS LANE5 100250MHz PCI Express JITTER ATTENUATOR RTM PCI EXPRESS LANE4 MGTclk J1/K1 RocketIO 112 A B MUX RTM PCI EXPRESS LANE3 RocketIO 113 INSPECTION PADS A B MUX (**) The ATCA FABRIC channels are routed from CHANNEL1 to CHANNEL12 by switches RocketIO 114 OPTICAL SFP A B MUX RTM PCI EXPRESS LANE2 (***) User SFP could be used as 1GEnet or PCIExpress DAQ without FABRIC

  10. MGT Layout MGT102A RocketIO ZONE3 (RTM) PCI Express Lane 0 MGT101B RocketIO ZONE3 (RTM) PCI Express Lane 1 MGT114B ZONE3 (RTM) PCI Express Lane 2 RocketIO MGT113A ZONE3 (RTM) PCI Express Lane 3 RocketIO MGT112A ZONE3 (RTM) PCI Express Lane 4 RocketIO 10Gb Crosspoint Switch 2.5Gb Buffer MGT110B ZONE3 (RTM) PCI Express Lane 5 RocketIO MGT103A RocketIO iSFP Cage (1GEthernet,PCI Espress,User …) (*) Clock in Cage To clock management (*) RocketIO FABRIC CHANNEL12 MGT105A TEST FABRIC CHANNEL11 FABRIC CHANNEL10 RocketIO MGT105B FABRIC CHANNELL9 TEST RocketIO FABRIC CHANNELL8 MGT106A FABRIC CHANNELL7 TEST The ATCA FABRIC is a DUAL STAR. This means that CHANNELS 1 of slot from 3 to 14 are are routed on CHANNEL1 to CHANNEL12 on HUB1 and CHANNELS 2 of slot from 3 to 14 are are routed on CHANNEL1 to CHANNEL12 on HUB2 FABRIC CHANNELL6 RocketIO MGT106B FABRIC CHANNELL5 TEST RocketIO FABRIC CHANNELL4 MGT109B FABRIC CHANNELL3 TEST FABRIC CHANNELL2 RocketIO (*) MGT109A (*) These cnannel must be routed on LLP cards, the others Channels are needed only on central switch. FABRIC CHANNELL1 (*) TEST

  11. AC VIAS N P N P P VIAS AC VIAS FABRIC 12 N N P AC P VIAS FABRIC 11 N N AC MGT105 A P N P N P AC AC MGT topology template AC N P N P AC P FABRIC 10 N N AC P AC P VIAS FABRIC 9 N N VIAS AC P MGT105 B N P N P AC

  12. AC VIAS N P N P P VIAS AC VIAS FABRIC 8 N N P AC P VIAS FABRIC 7 N N AC P N P N P MGT106 A AC AC MGT topology template AC N P N P AC P FABRIC 6 N N AC P AC P VIAS FABRIC 5 N N VIAS AC P N P N P MGT106 B AC

  13. AC VIAS N P N P N VIAS AC FABRIC 4 P N VIAS P N AC P FABRIC 3 N VIAS AC P N P N P MGT109 A AC AC MGT topology template AC N P N P N AC FABRIC 2 P N AC P AC N P VIAS N FABRIC 1 VIAS AC P N P N P MGT109 B AC

  14. P VIAS AC N P VIAS AC AC VIAS N MGT102 A P AC AC N P VIAS AC N MGT101 B N P N P N P N P LANE 2 LANE 1 PCI Express topology template LANE 4 LANE 3 N P N P N P N P N VIAS AC P N VIAS AC AC VIAS P MGT114 B N AC AC P N VIAS AC P MGT113 A

  15. PCI Express topology template LANE 6 LANE 5 N P N P N P N P P VIAS AC N P VIAS AC AC VIAS N MGT112 A N AC AC P N VIAS AC P MGT110 B N P P N

  16. ATCA Configuration and status TCK0 TMS0 TDI0 TDO0 Xc9500 pld TCK_CON TMS_CON TDI_CON TDO_CON MEZZANINE0 Connector 2.5 IOs TCK1 TMS1 TDI1 TDO1 TCK_PPC TMS_PPC TDI_PPC TDO_PPC Connected to Main FPGA IOs Fo FPGAs Update By Ethernet MEZZANINE1 2.5 IOs RTM/PPC TCK2 TMS2 TDI2 TDO2 MEZZANINE2 2.5 IOs CONF[1..0] MEZZANINE 0 CONF[1..0] MEZZANINE 1 CONF[1..0] MEZZANINE 2 TCK3 TMS3 TDI3 TDO3 CONF[1..0] MEZZANINE 3 2.5 IOs MEZZANINE3 FPGA_INIT/PROGRAM MEZZANINE 0 FPGA_INIT/PROGRAM MEZZANINE 1 TCK4 TMS4 TDI4 TDO4 FPGA_INIT/PROGRAM MEZZANINE 2 MAIN FPGA 2.5 IOs FPGA_INIT/PROGRAM MEZZANINE 3 FPGA_INIT/PROGRAM MAIN FPGA FPGA_INIT/PROGRAM TRG FPGA TCK5 TMS5 TDI5 TDO5 FPGA TRIGGER 2.5 IOs SEL PROGRAM MEZZANINE 0 SEL PROGRAM MEZZANINE 1 SEL PROGRAM MEZZANINE 2 SEL PROGRAM MEZZANINE 3 TCK6 TMS6 TDI6 TDO6 AUX_1 3.3 IOs SEL PROGRAM MAIN FPGA SEL PROGRAM TRG FPGA I2C_SCK TCK7 TMS7 TDI7 TDO7 AUX_2 3.3 IOs I2C_SCL

  17. PLD for Switch and Buffer Management LX15_FF348 10/204 TXSELA TXSELB RXSELA RXSELB 104 Signals FABRIC RX FABRIC TX ENA_A EQ_A0 EQ_A1 OSW_A ODE_A 14 Signals ENA_B EQ_B0 EQ_B1 OSW_B ODE_B x6 FABRIC RX FABRIC TX ENA_A EQ_A0 EQ_A1 OSW_A ODE_A 10/100 Signals 10 Signals ENA_B EQ_B0 EQ_B1 OSW_B ODE_B x4 I2C_SCK I2C_SCL

  18. ATCA I2C Layout and addressing Mezzanine 1 Address $00 Mezzanine 1 Address $00 Mezzanine 1 Address $00 Mezzanine 1 Address $00 Monitoring ADC Address $00 Serial EEPROM Address $00 Temp Sensor 1 Address $00 Address $00 Temp Sensor 2 Address $00 IPMB1 Temp Sensor 3 Address $00 Address $00 IPMB0 Jtag Supervisor Address $00 SWITCHS Supervisor Address $00 Address $00 Main Fpga RTM Address $00

  19. ATCA Power Supply 4x POWER ONE YS12S10 55W DC to DC Converter P3V3-5A 16.5W P3V3/P2V5 Linear Reg P2V5-1.5A VCCAUX Fpga 1 MEZZANINE 1 DC to DC Converter Fusing Filtering Protection Hot Swap P3V3-5A 16.5W MEZZANINE 2 P5V0/P2V5 Linear Reg P2V5-1.5A VCCAUX Fpga 2 -48V DC DC to DC Converter P5V0/P2V5 Linear Reg P2V5-1.5A P3V3-5A 16.5W MEZZANINE 3 VCCAUX MGT DC to DC Converter P5V0/P1V8 Linear Reg P1V8-0.5A P3V3-5A 16.5W MEZZANINE 4 PROMS ENABLE P5V0/P1V2 Linear Reg P1V2-0.5A VTTTXs ATC210 (210W) P12V-14.7A 176.7(160.6)W M48/P12 DC DC P5V0-6A 30W P5V0/P1V2 Linear Reg P1V2-0.5A VTTRXs P12/P5V0 DC DC M48V-4.0A 194.4(176.7)W P3V3_BOOT P3V3-7A 23.1W P12/P3V3 DC DC MAIN BOARD P12/P2V5 DC DC P2V5-7A 17.5W MAIN BOARD P12/P1V2 DC DC P1V2-7A 8.4W FPGAs CORE DC-DC Efficency is estimated at least 90% P12/P1V2 DC DC P1V2-4A 4.8W FPGA MGT P12/P1V8 DC DC P1V8-6A 10.8W MGT BUFFERS 6x POWER ONE YS12S10 55W

  20. I2C Mezzanines (2 wires) CMC1 Address $50 CMC2 Address $51 FPGA0 (FX100) Zarlink ctrl (9 wires) CLK PLL & switch ctrl (10 wires) CMC3 Address $52 MAIN DCDC ctrl (7 wires) CMC4 Address $53 FPGA2 (LX25)C Address $54 ZONE 1 connector IPMI addr (7 wires) IPMI A and B (4 wires) JTAG Switch IPMI A and B repeated (4 wires) RS232 Switch JTAG tap (4 wires) JTAG I2C Alarm & Warning (4 wires) MAN SW MAN SW I2C Temp sensors (3 wires) FPGA1 (LX15) DCDC_GOOD_* (9 wires) iSFP ctrl (16 wires) FPGA0 Temp MAX1617A Address $18 Temp Sens MAX6626 Address $48 ADC ctrl (9 wires) FPGA0 Temp MAX1617A Address $19 Temp Sens MAX6626 Address $49 FPGA0 Temp MAX1617A Address $4C Temp Sens MAX6626 Address $4A Temp Sens MAX6626 Address $4B

  21. MAIN FPGA (FX100) SFP Clock SFP Lanes FPGA0 Temp MAX1617A Address $18 CMC1 Address $50 FPGA1 Temp MAX1617A Address $19 CMC2 Address $51 FPGA2 Temp MAX1617A Address $4C CMC3 Address $52 Temp Sens MAX6626 Address $48 CMC4 Address $53 Temp Sens MAX6626 Address $49 FPGA SW LX15 Address ? I2C Multiplexer FPGA Ser. LX25 Address ? Temp Sens MAX6626 Address $4A JTAG mgm XC95xx Address ? Temp Sens MAX6626 Address $4B Prim. DC-DC ATC210 Address ? Mon. ADC ? Address ? IO Expander ? Address ? 1K EEPROM ? Address ?

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