ATCA LLP CARRIER BLOCK DIAGRAMS

ATCA LLP CARRIER BLOCK DIAGRAMS LAST UPDATE 09/05/2007

Master / Slave Structure SLOT A (n) MASTER/SLAVE CARD_PRESENT TCLK_PRESENT DATAPATH TRIGGER CLOCK SYNCs And DATA MANAGERS SWITCHES CLOCK AND SYNCS SLOT B (n+1) MASTER/SLAVE CARD_PRESENT TCLK_PRESENT DATAPATH TRIGGER CLOCK SYNCs And DATA MANAGERS TCLK CLOCK AND SYNCS

200Mhz Clock and Clock SYNC distribution MASTER 200MHz $07 – D0 SWITCH GTS $07 – D1 GTS_CLOCK CLOCK_ SYNC FANOUT VIRTEX4 LX25 DATA DISTRIBUTON PPC_CLOCK CORE SWITCH PLL $07 – D2 CLOCK_ SYNC SWITCH SEGMENT $08 – D1 100MHz PPC_CLOCK SMB INSP VIRTEX4 FX100 MAIN FPGA SEGMENT MGT CLOCK SYSTEM 100MHz 200MHz SLAVE 200MHz $07 – D0 SWITCH SEGMENT GTS_CLOCK $07 – D1 CLOCK_ SYNC FANOUT VIRTEX4 LX25 DATA DISTRIBUTON PPC_CLOCK SEGMENT SWITCH PLL $07 – D2 CLOCK_ SYNC SWITCH SEGMENT $08 – D1 100MHz PPC_CLOCK SMB INSP VIRTEX4 FX100 MAIN FPGA SEGMENT TCLK MGT CLOCK SYSTEM 100MHz 200MHz

100MHz clock with missed periods as SYNC event GTS ADCs CLOCK SYNC distribution MASTER SYNC_AUX GTS_SYNC GTS SYNC_RTN CORE FANOUT SWITCH SEGMENT SEGMENT SLAVE SYNC_AUX GTS_SYNC SEGMENT SYNC_RTN SEGMENT FANOUT SWITCH SEGMENT SEGMENT TCLK

Serializers SYNC signal distribution 10MHz clock signal (the patterns must be equal at any rising edge) MASTER TRIGGER FPGA GTS CORE FANOUT SWITCH SEGMENT MAIN FPGA SEGMENT SLAVE TRIGGER FPGA SEGMENT SEGMENT FANOUT SWITCH SEGMENT MAIN FPGA SEGMENT TCLK

Bcast & Msg Handler Serialized FROM REMOTE (TCLK) x6 LX25 FPGA 2 8 B_cast_data (7 downto 0) B_cast_str0 FANOUT TO MAIN FPGA, LOCALS MEZZANINES, AND REMOTE MEZZANINES (TCLK) SERIALIZERS 81 8 B_cast_str1 8 GTS Status (7 downto 0) GTS MEZZANINE MAIN FPGA LLP Status (7 downto 0) Msg_data (7 downto 0) Msg_str0 Msg_str1 x4 FROM REMOTE (TCLK) Concentrator SEG/CORE MEZZANINE LX25 FPGA 2 8 LLP Status (7 downto 0) TO REMOTE (TCLK) 8 Msg_data (7 downto 0) Msg_str0 8 Msg_str1

TRIGGER Handler serialized FROM REMOTE (TCLK) Trig_val (1 downto 0) LX25 8 Trig_Rej (1 downto 0) 8 FANOUT TO OTHERS DEST Lt_data (7 downto 0) Lt_Strobe 8 Tv_data (7 downto 0) GTS MEZZANINE Tv_Strobe Local_Trigger (1 downto 0) Trig_req (1 downto 0) Trig_req (1 downto 0) x4 TCLK CORE MEZZANINE MAIN FPGA

TRIGGER & BCAST Handler (parallel) Alignement BUS (3 lines) Trig_req (1 downto 0) 10pairs (20 lines) Trig_val (1 downto 0) Trig_Rej (1 downto 0) 8 Lt_data (7 downto 0) 8 Lt_Strobe 8 Tv_data (7 downto 0) GTS MEZZANINE cmc #1 8 Tv_Strobe TCLK 8 B_cast_data (7 downto 0) SERs / DESERs 81 B_cast_str0 B_cast_str1 8 GTS Status (7 downto 0) 8 8 8 8 266 / 448 ~50% of LX25_FF668 44 lines 44 lines 44 lines 44 lines CMC #2 CMC #3 CMC #4 FX100

Using 1 16 bit port : 128 words/event 256 bytes/event 6 channels  1536bytes 16bit bus @ 100MHz Need 7.68µs (20µs avaible @ 50KHz) 1536*4 = 6144 byte/Event 16bit bus @ 200MHz Need 15.36µs (20µs avaible @ 50KHz 8 pairs ; 16 I/O Serializer Data_A (15 downto 0) Deserializer Serializer 18bit 18bit Serializer Empty_A Serializer Data_Ready_A 1Mx18 DPRAM Data_Request_A Data_A (15 downto 0) Empty_A 20bit 20bit Data_Ready_A Data_Request_A Max 325 Events stored 6.5msec@50KHz Data Rate Required 307.2 Mb/sec @50KHz X4 Mezzanines Data readout engine

MGT Clocking Layout (***) User SFP could be used as 1GEnet or PCIExpress DAQ without FABRIC ATCA FABRIC CH12 RocketIO 101 A B MUX ATCA FABRIC CH11 MGTclk M34/N34 ATCA FABRIC CH10 RocketIO 102 200MHz GTS Clock MUX A B ATCA FABRIC CH09 ATCA FABRIC CH08 MGTclk AP28/AP29 RocketIO 103 MUX A B PHASE LOCKED ATCA FABRIC CH07 ATCA FABRIC CH06 RocketIO 105 100MHz GTS Clock A B MUX ATCA FABRIC CH05 ATCA FABRIC CH04 RocketIO 106 LOCAL 100MHz A B MUX ATCA FABRIC CH03 RocketIO 109 ATCA FABRIC CH02 A B MUX ATCA FABRIC CH01 MGTclk AP3/AP4 RocketIO 110 A B MUX 100250MHz PCI Express JITTER ATTENUATOR MGTclk J1/K1 RocketIO 112 A B MUX PCI Express SFP ATCA FABRIC CH15 RocketIO 113 A B MUX ATCA FABRIC CHxx RocketIO 114 ATCA FABRIC CH13 OPTICAL SFP A B MUX ATCA FABRIC CH14

ATCA Zone1 IPMI IPMI Address IPMI A FPGA0 Temp MAX1617A Address $18 IPMI B FPGA1 Temp MAX1617A Address $19 MAIN FPGA (FX100) FPGA2 Temp MAX1617A Address $4C FPGA1 Sw LX25 Address $60 Fast Ethernet Temp Sens MAX6626 Address $48 FPGA2 Trigger LX25 Address $61 Temp Sens MAX6626 Address $49 I2C Multiplexer I2C Multiplexer SFP Clock SFP Lanes Temp Sens MAX6626 Address $4A Temp Sens MAX6626 Address $4B CMC1 Address $50 I2C bus layout CMC2 Address $51 CMC3 Address $52 uProcassor DC-DC ATC210 Address ? CMC4 Address $53

ATCA Zone1 IPMI IPMI Address IPMI A MANUAL SW IPMI B MAIN FPGA (FX100) JTAG SWITCH RMT JTAG JTAG Connector (Front Panel) Fast Ethernet CONF[1..0] SEL PROGRAM [1..0] I2C Multiplexer TCK TMS TDI TDO INIT X7 (4 Mezzanines + 3 FPGAs) Slow control layout (JTAG Management)

TCLK Port Layout

ATCA Power Supply (maximum) LINEAR REGULATORS P3V3-0.1A IC2 P5V0/P3V3 Linear Reg P1V8-0.4A ZARLINK_VCC DC-DC ARTESYN DC-DC NATIONAL P3V3_ZLK IC106 P1V8_ZLK Fusing IC5 M48/P12 DC DC P12V P1V8-0.5A IC99 P5V0/P1V8 Linear Reg P3V3-5A 16.5W DC to DC Converter MEZZANINE 1 IC6 PROMS -48V DC P1V8_FLASH0 18.2W P3V3_CMC1 P1V8_FLASH1 P1V8_FLASH2 IC54 VCCAUX MGT IC100 IC78 P3V3-5A 16.5W DC to DC Converter MEZZANINE 2 P5V0/P2V5 Linear Reg P2V5-0.05A M48V-4.2A 200W P3V3_BOOT 18.2W P3V3_CMC2 P2V5A VCCAUX Fpga 1 IC108 P3V3-5A 16.5W DC to DC Converter IC45 P5V0/P2V5 Linear Reg P2V5-1.0A MEZZANINE 3 18.2W P3V3_CMC3 P2V5_AUX_FPGA0 HS ENABLE IC110 P3V3-5A 16.5W DC to DC Converter MEZZANINE 4 IC42 P5V0/P2V5 Linear Reg VCCAUX Fpga 2 P2V5-1.0A 18.2W P3V3_CMC4 P2V5_AUX_FPGA2 IC16 P3V3-7A 23W P12/P3V3 DC DC MAIN BOARD P12V-14.6A 181W IC49 P5V0/P1V5 Linear Reg P3V3-0.2A 25.3W PLL_VCC P3V3 P3V3A IC94 P12/P2V5 DC DC P2V5-7A 17.5W MAIN BOARD IC95 P5V0/P3V3 Linear Reg P3V3-0.6A SFP Power Supply 19.3W P2V5 P3V3_SFP_LANES IC92 P3V3_SFP_CLOCK P1V2-9A 11W P12/P1V2 DC DC FPGAs CORE IC26 P2V5-2A 5W P2V5/P1V8 Linear Reg SWITCH MICREL 10.8W P1V2 P2V5A_SW 2.0A (10W) IC86 P2V5/P1V8 Linear Reg P0V8-0.8A DC-DC POWER ONE P1V8_VCCO IC10 IC53 P12/P5V0 DC DC P2V5/P1V8 Linear Reg P0V8-0.8A DPRAM_VREF 52.6W P5V VREF_DPRAM P5V0-8.6A 47.8W IC24 IC57 P1V2-5A 6W P2V5/P1V8 Linear Reg P1V8-0.8A P5V0/P1V2 DC DC FPGA MGT DPRAM_VCC 6.6W P1V25A P1V8_DPRAM IC59 P1V8-4.2A 7.5W P1V5-2.5A IC51 IC58 P2V5/P1V5 Linear Reg P5V0/P1V8 DC DC VTTTXs MGT BUFFERS 8.3W VTTTX_TILE1 P1V8A VTTTX_TILE2 IC15 IC48 P1V5-0.2A P2V5-4.8A 15.8W P2V5/P1V5 Linear Reg P5V0/P3V0 DC DC VTTRXs 17.4W VCCB VTTRX DC-DC Efficency assumed at least 90%

Case 1 : PCIExpress PCIExpress 1Mx36 DPRAM PCIExpress 1Mx36 DPRAM 1Mx36 DPRAM PCIExpress PCIExpress 1Mx36 DPRAM 1Mx36 DPRAM TCLK Bus PCIExpress PCIExpress 1Mx36 DPRAM 1Mx36 DPRAM PCIExpress PCIExpress 1Mx36 DPRAM ADCs 1Mx36 DPRAM PCIExpress PCIExpress PRE PROCESSING 1Mx36 DPRAM 1Mx36 DPRAM PCIExpress PCIExpress 1Mx36 DPRAM 1Mx36 DPRAM PCIExpress PCIExpress 1Mx36 DPRAM 1Mx36 DPRAM 1Mx36 DPRAM PCIExpress PCIExpress

Case 2 : 1G Ethernet switch TCLK Bus 1Mx36 DPRAM 1Mx36 DPRAM 1Mx36 DPRAM 1Mx36 DPRAM GEthernet Switch EB FARM 1Mx36 DPRAM 1Mx36 DPRAM 1Mx36 DPRAM 1Mx36 DPRAM 1Mx36 DPRAM 1Mx36 DPRAM 1Mx36 DPRAM ADCs 1Mx36 DPRAM 1Mx36 DPRAM 1Mx36 DPRAM PRE PROCESSING

Case 3 : PCIExpress (full mesh) PCIExpress 1Mx36 DPRAM PCIExpress 1Mx36 DPRAM 1Mx36 DPRAM PCIExpress PCIExpress 1Mx36 DPRAM 1Mx36 DPRAM PCIExpress PCIExpress 1Mx36 DPRAM 1Mx36 DPRAM PCIExpress PCIExpress 1Mx36 DPRAM 1Mx36 DPRAM PCIExpress PCIExpress 1Mx36 DPRAM 1Mx36 DPRAM PCIExpress PCIExpress 1Mx36 DPRAM 1Mx36 DPRAM PCIExpress PCIExpress 1Mx36 DPRAM 1Mx36 DPRAM 1Mx36 DPRAM PCIExpress PCIExpress

ATCA LLP CARRIER BLOCK DIAGRAMS