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Muon Track-Finder Trigger

Muon Track-Finder Trigger. Darin Acosta University of Florida June, 2002. Muon Track-Finding. Link trigger primitives into 3D tracks Measure p T , , and  in non-uniform fringe field Send highest quality candidates to Global L1.

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Muon Track-Finder Trigger

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  1. Muon Track-Finder Trigger Darin Acosta University of Florida June, 2002

  2. Muon Track-Finding • Link trigger primitives into 3D tracks • Measure pT, , and  in non-uniform fringe field • Send highest qualitycandidates to Global L1 • Partitioned into 60° sectors that align with DT chambers  

  3. CSC Muon Trigger Scheme EMU Trigger On-Chamber Trigger Primitives Muon Port Card(Rice) 3-D Track-Finding and Measurement Trigger Motherboard(UCLA) Strip FE cards Sector Receiver/ Processor(U. Florida) LCT OPTICAL FE SP SR/SP MPC LCT TMB 3 / port card FE 2 / chamber 3 / sector Wire LCT card Wire FE cards In counting house RIM CSC Muon Sorter(Rice) RPC Interface Module RPC DT 4 4 4 Combination of all 3 Muon Systems Global L1 Global  Trigger 4

  4. Prototype version tested Fall 2000: New version (SR/SP combined) Scope of CSC Track-Finder Baselined with 24 crates, reduced to 6 in 1998, now 1:

  5. DAQ System (VME, Bit3 Controller, PC running Windows NT) 100m Optical Links Custom Back plane Port Card Sector Receiver Sector Processor FIFO FIFO FIFO FIFO FIFO FIFO Prototype Track Finder Tests • Focus during FY 2000 was on producing and testing prototypes of all Track-Finder components (except the CSC Muon Sorter) • Sector Processor: UFlorida • Sector Receiver: UCLA • Muon Port Card: Rice • Clock and Control Board: Rice • Channel-Link backplane: UFlorida • Integration tests of the complete system yielded 100% agreement between hardware and software for random and simulated physics events Results included in Trigger TDR

  6. Sector Receiver Prototype UCLA Optical Receivers and HP Glinks SRAM LUTs Receives and formats track segment data Front FPGAs Back FPGAs

  7. Sector Processor Prototype Final Selection UnitXCV150BG352 Extrapolation UnitsXCV400BG560 Florida Links track segments into 3D tracks, selects best three tracks, measures momentum 12 layers 10K vias 17 FPGAs 12 SRAMs 25 buffers Assignment UnitsXCV50BG256 &2M x 8 SRAM Track Assemblers256k x 16 SRAM Bunch Crossing AnalyzerXCV50BG256

  8. 1st Track-Finder Crate Tests Clock Control Board (Rice) Sector Receiver (UCLA) Muon Port Card (Rice) Sector Processor (Florida) Bit3 VME Interface Very successful, but overall CSC latency was too high -- New design in 2001 improves latency Custom ChannelLink Backplane (Florida) Prototype crate for original six crate design 100m optical fibers

  9. Single Track-Finder Crate Design with 1.6 Gbit/s optical links Reduces processing time from 525 ns (old design) to 175 ns Total Latency ~ 15 Bx (from input of SR/SP card to output of MS card) Crate Power Consumption ~ 1000 W • 16 Optical connections per SR/SP card Custom Backplane for SR/SP  CCB and MS connection New Track-Finder Crate Design SR/SP Card (3 Sector Receivers + Clock and Control Board Sector Processor) SR SR SR SR SR SR SR SR SR SR SR SR CCB ° MS / (60 sector) / / / / / / / / / / / SP SP SP SP SP SP SP SP SP SP SP SP BIT3 Controller From MPC (chamber 4) Muon Sorter From MPC (chamber 3) From MPC (chamber 2) From Trigger Timing & Control From MPC (chamber 1B) From MPC (chamber 1A) ToGlobal Trigger To DAQ

  10. CSC Track Finder Backplane Florida Standard VME 64x J1/P1 backplane GTLP backplane avoids latency penalty of previous Channel-Link backplane (~3BX) SRSP 1 SRSP 2 SRSP 3 SRSP 4 SRSP 5 SRSP 6 Clock and control Muon sorter SRSP 7 SRSP 8 SRSP 9 SRSP 10 SRSP 11 SRSP 12 Standard VME J2/P2 backplane Rice Custom GTLP 6U backplane Design Approved –Technology same as EMU peripheral crates These SRSP feedthru connectors are for DT information exchange via transition board

  11. SR/SP 2002 Board Layout

  12. SR/SP 2002 Design Status • Schematics nearly complete: • Sector Receiver Front FPGAs (5 total) • Choice: XC2V1000-FF896C with 432 user I/Os • Sector Processor Main FPGA • Choice: XC2V4000-FF1152C with 824 user I/Os • Placed on mezzanine card (design started) • Firmware written in “Verilog++”, validated by simulation • VME & control interface FPGA • Choice: XC2V250-FG456C with 200 user I/Os • DAQ Interface FPGA • Choice: XC2V250-FG256C with 172 user I/Os • SRAM: • 51 SRAM chips (>64MB) for Look-up functionality • Layout to commence soon • Board will be dense! (Merger of 4 boards, but I/O ~same)

  13. New Design Reduces Latency First prototype dataflow Pre-production prototype data flow From Muon Port Cards From Muon Port Cards Optical receivers Optical receivers Front FPGAs 1 Front FPGAs 1 Sector Receiver st.4 Sector Receiver st.1 Sector Receiver st.2,3 To DT Lookup tables 1 Lookup tables 1 SR/SP board Channel link transmitters 0 Bunch crossing analyzer (not implemented) 4 Channel link receivers 1 Extrapolation units Latency Latency Bunch crossing analyzer (not implemented) 1 2 9 Track Assembler units Sector Processor FPGA Extrapolation units 3 1 Final selection unit 3 best out of 9 Pt precalculation for 9 muons 9 Track Assembler units (memory) 2 Final selection unit 3 best out of 9 3 1 Output multiplexor Sector Processor Pt precalculation for best 3 muons 3 1 Pt assignment (memory) Pt assignment (memory) 2 Total: 7 BX Total: 21 BX To Muon Sorter To Muon Sorter

  14. New Muon Sorter Design (Rice) • Reduced to single board -- reduces latency, cost VME J1 CONNECTOR 9U * 400 MM BOARD VME INTERFACE LVDS DRIVERS CONNECTORS TO GMT CCB INTERFACE SORTER LOGIC INPUT AND OUTPUT FIFO SP1 SP2 SP3 SP4 CABLES TO GLOBAL MUON TRIGGER CRATE CUSTOM BACKPLANE SP5 SP6 SP7 SP8 New: Will use commonXilinx mezzanine cardwith Sector Processor SP9 SP10 SP11 SP12 GTLP TRANSCEIVERS

  15. Sorter FPGA SP 1 DFF MUON 1 DFF MUX MUX PIPELINE MUON 1 VME LUTs FIFO FIFO DFF VME MUX PIPELINE MUON 2 VME VME DFF MUON 2 FIFO LUTs FIFO DFF MUX PIPELINE MUON 3 VME VME VME FIFO DFF MUON 3 . LUTs SP 2 . FIFO . VME VME DFF MUON 4 SP 12 . . . LUTs VME FIFO 144 SORTER “4 OUT OF 36” VME CCB VME CCB INTERFACE

  16. CCB for Track Finder Crate • Same CCB for peripheral (EMU) and Track Finder crates • 20 sets (main 9U board + Altera-based mezzanine card) have been fabricated so far • 15 boards are assembled and tested • 2 boards will be used for Track Finder tests (UF&Rice) TTCrx mezzanine board

  17. Personnel • Professors • Darin Acosta (Florida), Robert Cousins (UCLA), Paul Padley (Rice) • Postdocs • Song Ming Wang (Florida), Slava Valouev (UCLA) • Students • Bobby Scurlock (Florida), Jason Mumford (UCLA) • Engineers • Alex Madorsky (Florida), Mike Matveev (Rice), Ted Nussbaum (Rice) • Collaborating engineers (all PNPI) • Victor Golovtsov, Lev Uvarov

  18. Conclusions • First Track Finder system prototyped successfully in Fall 2000 • Exact match to CMS OO simulation package • Second generation pre-production prototype is well underway with significant improvements • Present and future activities • 2001: R&D on optical links, FPGA logic, memory look-ups, backplane technology, and DAQ readout • 2002: build the 2nd generation prototype • 2003: test with multiple CSC chambers, cosmic rays and/or structured beam, tweaks for final design (if necessary) • 2004: full production • 2005: installation • No trouble expected: all-digital system with off-the-shelf components, well-defined internal and external interfaces, and a stable and capable engineering team

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