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Drift Tube Trigger Track Finder

Drift Tube Trigger Track Finder. Vienna, Madrid, Bologna The Drift Tube Trigger Track Finder system (DTTF) consists of: PHTF - Phi Track Finder Sector Processor (72 boards) - Vienna - new name (formerly called DTTF) ETTF - Eta Track Finder (12 boards) - Madrid, Vienna

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Drift Tube Trigger Track Finder

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  1. Drift Tube Trigger Track Finder • Vienna, Madrid, Bologna • The Drift Tube Trigger Track Finder system (DTTF) consists of: • PHTF - Phi Track Finder Sector Processor (72 boards)- Vienna • - new name (formerly called DTTF) • ETTF - Eta Track Finder (12 boards) • - Madrid, Vienna • WS - Wedge Sorter (12 boards) • - Bologna • TIM - Timing Module (6 boards)- Vienna • - same design as for Global Trigger • DAQU - DAQ output unit (1+6 boards)- Vienna • - muon data to be stored on tape by DAQ • DT/CSC Transition Board (24 boards)- Vienna • - information exchange between DT and CSC • Output Test Board (1 board) -Vienna • - only for testing

  2. Status of PHTF • - Function Evaluation Prototype ready • Long term tests performed • Tests with ORCA simulation data • One bit error in one track segment (probably broken line in an internal layer) • One assignment error • Clock phase control: 3 states instead of 5 • Further investigations in progress • - Four additional PHTF boards are in production • Final adjustments were made to layout • Individual JTAG access added for each BGA chip • (important for the initial phase) • PCB with better thermal parameters chosen

  3. Changes to the ETTF algorithm • Matching patterns recalculated (2002) • Number of patterns reduced by 25%: Fit neatly into two FPGAs • Pseudo-rapidity assignment: • Region covered goes from (-1.3, 1.3) to (-1.2,1.2) • Assigned eta now in Station 2 to be consistent with RPC • Quality ordering revised (based on simulation) • Prefers one extra segment rather than a high-quality one • But might be reconsidered according to June test beam results • New algorithm tested with ORCA_6 • New reduced set of patterns slightly more efficient (91% to 93%)

  4. Status of ETTF • VDHL model done and tested • High-statistics ORCA sample prepared to check VHDL model in event-by-event basis (will follow) • Board design ready, 2 boards in production • 8 layers • 2 big and 5 small FPGAs – fully reconfigurable (except the connections) • same input connection as for PHTF • Integration test with PHTF will follow

  5. ETTF board block diagram Address of Tracks found by negative side PHTFs 3x2x5 bit on Backplane Optical Inputs Input Synch. -2 21 bit hit 21 bit quality 7+7 21 bit hit 21 bit quality Input Synch. -1 ETTF-N 2x3x6 bit Eta 7+7 1+1 21 bit hit 21 bit quality Input Synch. 0 2+2 Output driver 4x3x6 bit Eta 7+7 To Wedge Sorter 21 bit hit 21 bit quality Input Synch. +1 7+7 ETTF-P 2x3x6 bit Eta 21 bit hit 21 bit quality Input Synch. +2 7+7 Address of Tracks found by positive side PHTFs 3x2x5 bit on Backplane

  6. Status of Wedge Sorter (Bologna) Board received in August. Description of functionality: http://montan.home.cern.ch/montan/DT_WedgeSorter_May2003.pdf Almost finished preliminary electrical test (power, connections, etc). Ready to start the first JTAG tests and preparing the test jig for a full functionality test by using Pattern Units.

  7. Status of other DTTF boards • - DT/CSC Transition Board • Board ready, partly tested • FPGA with Range Correction LUT filled in by 1:1 mapping • Connection test next week • Output Test Board • Board ready, participates in tests • Allows to read out DTTF results in real time with logic analyzer • or Input Buffer Board • Plugged to the Wedge Sorter back side • selectable PHTF output • GTL+ termination pluggable (remove when WS is in use) • - DAQ Output Board • first design steps made

  8. DTTF Milestones and Schedule DATE ITEM STATUS May 2003: PHTF function evaluation prototype tested basically done June 2003: DT/CSC overlap test now: Sept. 2003 * July 2004: PHTF pre-production prototype (PPP) done on schedule * Dec. 2004: PHTF production done on schedule June 2003: ETTF design donedone Dec. 2003: ETTF boards produced on schedule * Sep. 2003: DTTF prototype integration (PHTF,ETTF,WS)foreseen: Dec. 2003 * June 2003: Wedge Sorter prototype done ready for final tests * July 2004: Wedge Sorter production done on schedule * Nov. 2003: Barrel Sorter prototype done now: Jan. 2004 * July 2004: Barrel Sorter production done on schedule (most recent milestone indicated by *)

  9. Timing Module Data source card PHTF Result read back card DTTF Test Crate (front)

  10. Optical link emulator Output Test Board DT/CSC Transition Board DTTF Test Crate (rear)

  11. Global Muon Trigger Overview 252 MIP bits252 Quiet bits 4 m RPC brl 4 m DT Inputs:8 bit f, 6 bit h, 5 bit pT, 2 bits charge, 3 bit quality,1 bit halo/eta fine-coarse Best 4 m 4 m CSC Output:8 bit f, 6 bit h, 5 bit pT, 2 bits charge/synch, 3 bit quality,MIP bit, Isolation bit 4 m RPC fwd

  12. 1 GMT Logic Board GMT in the Global Trigger Crate 3 Pipeline Sync. Boards 6-channel prototype available Conceptual design readyFPGAs being designed Special wide input board parallel to front panel Global Trigger Crate 4 DT/CSC + 8 RPC muons

  13. GMT progress since September 2002

  14. FPGA Development for GMT Developer VHDL for look-up tables generated byLUT Framework from C++representation VHDL VHDL VHDL Cadence NCSIM CVS Server Behavioral simulation Synplify 7.3 Synthesis Automated testsverify functionality after every changecross-check with C++ simulation Concurrent Versions Systemto manage VHDL code Xilinx ISE 5.2.03i Implementation Cadence NCSIM “Build System”most of design flow scripted with Makefiles Gate level simulation Chip configuration

  15. Xilinx XC2V3000 432 chip inputs/outputs 96/96 18 kbit memory blocks used Developed VHDL model Simulated behavioral model & cross-checked with ORCA (NC-SIM) Synthesized using Synplify 7.21 Implemented with Xilinx ISE 5.2.03 Simulated chip-level VHDL &cross-checked with ORCA (NC-SIM) MIP and ISO Assignment FPGA’s GMT Logic Board

  16. Xilinx XC2V3000 464 chip inputs/outputs 92/96 18 kbit memory blocks used Developing VHDL model 95 % complete Synthesized using Synplify 7.21 Implemented with Xilinx ISE 5.2.03 75% of chip resources used To be done Complete VHDL model Synthesize/Implement final version Simulate gate level model Logic FPGA’s GMT Logic Board

  17. Generic Handling of GMT Lookup-Tablesprojection, h-conversion, sort-rank, merge-rank, … LUT Generator Application (C++) ORCA simulation (C++) Global Muon Trigger Simulation Save() GMT LUT X Save Method GMT LUT Y Save Method GMT LUT X Lookup Method Lookup() GMT LUT Y Lookup Method Scales, Parameterizations Scales, Parameterizations config file LUT file LUT file C++ classesrepresent LUT function config file LUT2HW tool (C++) XCO DPM RAM definition COE memorycontents Used in ORCA Simulation of GMT Used to generate all files need for firmware implementation • Function calculated at runtime • Memory efficient • All code in ORCA CVS repository Xilinx CoreGenerator VHDL wrapper .EDN .VHD .MIF

  18. GMT consists of 3 pipeline synchronizing boards … prototype available 1 GMT logic board … logic design completed FPGA design for GMT logic board in progress Input FPGA (4x) … logic design completed MIP and ISO assignment unit (2x) … firmware completed (brl+fwd) GMT logic FPGA (2x) … firmware 95% complete (brl+fwd) Sorter FPGA (1x) … logic design completed Milestones (unchanged since Apr 2002) (Dec 01)Dec 02: logic design completed … completed (Dec 02)Dec 03: FPGA design done … progress as planned (Dec 03)Jun 04: GMT available … progress as planned (Jun 04)Oct 04: GMT tested … progress as planned Oct 04: GMT integration tests start … planned on time Jan 05: GMT integration tests completed … planned on time GMT Hardware Status

  19. 4 U Cross Flow Fan Rack Layout according to CMS Standard with Monitoring Unit Rack: CMS-DISIR-IG-0002 v.2 (EDMS Id: PCI-VME link 114226) 2 U Heat Exchanger 1U=1.75“=44.45mm 56U racks, w=60cm, 4 Tracker Emulators,.. depth=90cm, h=256cm 9U/6U crate 8 Emulator cables other 6U_boards (standard VME backplane) 2 U Fan Unit JTAG 2 U Heat Exchanger 16 DT,CSC,RPC muon cables GMT, GT, TCS 12 cables MIP/QUIET bits 9U crate (non-standard backplane) 7 cables Calo trigger data +1 free cable trigger data 9kW cooling power 47U used 2 U Fan Unit 32 TTC_data (L1A,cmd) 3kW per crate 2 U Heat Exchanger 32 Subdetector STATUS cables Conversion boards 8 DAQ STATUS cables 9U/6U crate (Fast signals,...) 8 PTC STATUS cables (standard VME backplane) 2 U Fan Unit 2 U Heat Exchanger 2 S-links 2 U Air Flow Guide Note: PCs will actually be moved to top of rack PCs outside Air Flow DAQ -PC 2 opt. DAQ links less than 9 U used Online-PC Global Trigger Ethernet 56U Rack PrivateTest-PC A.Taurok 28 May 2003 Global Trigger Rack

  20. Global Trigger Crate All boards on front side. Boards arranged for minimum cable length.

  21. Global Trigger Prototype Crate GTL_CONV VME interface PSB PSB GTL6U

  22. PSB-6U Prototype Board Synchronisation and monitoring of trigger data PSB6U only for the Prototype Crate VME interface ROP for DAQ Input module SYNC chips MEMORY

  23. new PSB_IN80 for PSB-6U Registers for 40 80 MHz conversion 40, 80 MHz CLK drivers DS92LV16 receivers DS92LV16 transmitter for tests Infiniband connectors

  24. GTL Conversion Board GTL_CONV is used only in the Prototype Crate VME interface VME to GTL6U +1.5V supply 80MHz GTL+ signals Channel Link signals ChannelLinkRec CONV chips

  25. VME COND chips 4 muons 4x4 calo objects GTL+ signals REC chips GTL-6U Logic Board (right side) GTL6U will be used in the prototype crate as well as in the final GT-crate Calculates 64 trigger algorithms

  26. TIM chip new TIM-6U Timing Module TIM-6U will be used in the prototype as well as in the final GT and DTTF crates. VME TTCrx CLOCK circuits LVDS drivers CLK, BCRES, L1A, RESET to each VME slot Front Panel

  27. FDL-9U Final Decision Logic A.T. 21.2.03 VME FDL chip on MEZZ896 ALGO bits to DAQ ALGO bits to EVM Techn.Trigger bits from PSB ALGO bits from GTL Final OR bits to TCS

  28. TCS-9U Central Trigger Control Board VME TCS status to 8 DAQ part‘s L1A,... to 32 TTCvi FastSigs from 8 Emulators EVM+DAQ records FastSigs 24 part‘s + 8DAQ part‘s TCS_MON chip TCS chip Clock

  29. Mezzanine Board (MEZZ896) XC2V2000-4FF896C 50 Ohm connectors bottom side top side BGA: 1mm pitch, track width=83 mm MEZZ896 will be used in TCS-9U and FDL-9U

  30. TTC units SIGNAL GENERATOR TTCvi TTCvx 100kHz-1GHz Global ECL AC clk_in clk_out Calorimeter Global Trigger clk_out clk_in Trigger orbit _out PSB + TIM IM TTC A PSBin80 A B rx optical B ECL fibre trans CLK clk_x NIM board return BGo command: 0001 bcres NIM rec orbit _x clk diff PECL Infiniband cable 1m / 5m Serial Link 1280 Mbps GCT-trigger data GCT/GT integration test setup Bristol + Vienna groups, Vienna, July 2003

  31. GCT/GT integration test results and plans Link latency 50 ns with 1m cable, 65 ns with 5m cable. Data exchange 64 bits per 25 ns sent over one two-pair Infiniband cable. Different sets of patterns have been programmed at the transmitter end of the link and successfully read from a memory on the PSB. Clock PLL-based clock drivers to stabilize the TTC clock signals can be used. Long term stability Full test still to be made. 20000 LHC orbits equivalent to 5 . 109 bit cycles tested. Further tests Planned in Vienna with boards from Bristol in autumn 2003.

  32. GT on-line software C++ test programs exist to run the following boards both stand-alone and as a system : PSB-6U, GTL-CONV, GTL-6U, TIM-6U, TTCvi. The programs are being implemented as XDAQ-plugins. The GT setup definition is planned in .xml format, also to be used by ORCA. We are working on the SETUP program, including on a concept with a GUI.

  33. Global Trigger Status and Milestones Sept. 2003 • Custom Backplane for VME 9U crate • 6U Prototype: Channel Links ... existsMS 03/02 • 9U Backplane: 80MHz GTLp and Channel Links, ... design in progress MS 03/03 09/03 12/03 • PSB Input board (synchronisation, monitoring) • 6 channel 6U Prototype: Channel Link receivers... board tested MS 03/02 • PSB-IN80:DS92LV16serial receivers... board tested • 12 channel board: memories inside FPGAs ...conceptual designMS 06/04 • GTL Logic board: • Conversion board for prototype ... board tested MS 03/02 • GTL-6U prototype: 20 channels …hardware is testedMS 06/03 • Signal transfer tested with test patterns -> ok … working on firmware • XDAQ compatible test program in C++ exists • Loading of conditions not tested yet (software under development) • GTL-9U board: 32 channels ...conceptual designMS 11/04 • 4, 4 isol. e/, 4e/, 4 central jets, 4 fwd jets, 4 t-jets, SET, ET mis, HT, 12 jet counts • TIM Timing board ... board testedMS 06/03  09/04 • 6U size, TTCrx, clock and L1A distribution, also used by DTTF; working on version for new TTCrx • MEZZ896 • Mezzanine boards(used on TCS-9U, FDL-9U)... boards produced MS 06/03 • FDL-9U Final Decision board... design in progress MS 06/03 11/03  02/04 • TCS-9U Central Trigger Control board... Layout finished MS 04/03 09/03  12/03 • GTFE-9U Readout board... conceptual design MS 12/03 03/04  02/05 Milestones updated

  34. Global Muon Trigger FPGA design  12/03 Board production  06/04 GMT system tests  01/05 Production, Full Chain and Slice Tests, Integration Global Trigger Global Trigger PROTOTYPE BACK-6U ok PSB-6U ok PSB-IN80 ok GTL-CONV ok GTL-6U hardware tested (Milestone 6/03) TIM-6U done (Milestone 6/03) - prototype will be used as spare module for final system Integration test with GCT done (July 2003) GTL-6U hardware ok TIM-6U  09/04 (version for new TTCrx) TCS-9U  09/03  12/03 BACK-9U  09/03  12/03 FDL-9U  11/03  02/04 GTFE  03/04  02/05 PSB-9U  06/04 System test (full chain) of 20-channel GT (without GTFE)  06/04 Integration of GT/GMT with DAQ  01/06 Slice tests performed in Vienna as boards become available. Installation and commissioning in USC55 planned in phase with other subsystems (GCT, regional muon trigger systems) during second half of 2005. GTL-9U  11/04 GT system tests  6/05

  35. Acknowledgements Thanks to the following people for providing transparencies: J. Erö, J. F. de Trocóniz, Ch. Deldicque (DT Track Finder) A. Montanari (Wedge Sorter) H. Sakulin (Global Muon Trigger) A. Taurok (Global Trigger hardware) J. Strauss (Global Trigger software)

  36. Summary of main progress • DTTF (Bologna, Madrid, Vienna) • f track finder function evaluation prototype produced and tested (Vienna) • h track finder VHDL model and board design ready (Madrid, Vienna) • Wedge Sorter prototype available (Bologna) • Other DTTF boards produced (Vienna) • GMT (Vienna) • FPGA logic design close to completion • GT (Vienna) • Logic board produced and tested • Timing module produced and tested • Layout of TCS module finished • All systems (Bologna, Budapest, Madrid, Vienna) • On-line software under development • ORCA software updated in parallel • CMS-Note on SUSY level-1 trigger efficiencies practically ready

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