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Global Muon Trigger

Global Muon Trigger. Slides from Hannes Sakulin. NEW. NEW. Global Muon Trigger Overview. 252 MIP bits 252 Quiet bits. 4 m RPC brl. 4 m DT. Inputs: 8 bit f , 6 bit h , 5 bit p T , 2 bits charge, 3 bit quality, 1 bit halo/eta fine-coarse. Best 4 m. 4 m CSC.

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Global Muon Trigger

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  1. Global Muon Trigger Slides from Hannes Sakulin

  2. NEW NEW Global Muon Trigger Overview 252 MIP bits252 Quiet bits 4 m RPC brl 4 m DT Inputs:8 bit f, 6 bit h, 5 bit pT, 2 bits charge, 3 bit quality,1 bit halo/eta fine-coarse Best 4 m 4 m CSC Output:8 bit f, 6 bit h, 5 bit pT, 2 bits charge/synch, 3 bit quality,1 bit MIP, 1 bit Isolation 4 m RPC fwd

  3. GMT consists of 3 pipeline synchronizing boards (PSBs)… prototype available 1 GMT logic board… logic design completed All boards housed in GT crate & rack … see GT talk FPGA design for GMT logic board in progress Input FPGA (4x)… logic design completed GMT logic FPGA (2x)… logic design completed MIP and ISO assignment unit (2x) … FPGA firmware completed Sorter FPGA (1x)… logic design completed VME interface & read-out-processor Milestones (unchanged since April 2002) Dec 2002: logic design completed… completed Dec 2003: FPGA design done… progress as planned Jun 2004: GMT available Oct 2004: GMT tested GMT Hardware Status

  4. Improved functionality Additional cancel-out units in overlap region (DT-fwdRPC, CSC-brlRPC) Ghosting reduced below 0.1 % in 0.9 < |h| < 1.15 More robust w.r.t. shifts of RPC vs. DT/CSC h-boundary Improved pT-assignment for matched pairs Minimum pT method used in most regions  powerful rate reduction In regions where minimum-pT decreases plateau efficiency  select pT by rank Development of tools Software for generation of look-up-table contents In MIP/ISO assignment FPGA: 4 types of LUTs x 16 instances per chip Software for generic handling of look-up-tables withautomatic generation of all files for implementation of Xilinx firmware Generation of test files from ORCA & VHDL test bench Development of FPGA firmware MIP & ISO assignment FPGA barrel done & verified against ORCA GMT Progress in Last 6 Months

  5. Generic Handling of GMT LUTs C++ L1MuGMTLUT Class L1MuGMTLUT inputs, outputs, instances, contents Lookup(), Load(), Save() WriteVHDL() WriteHTML() virtual AlternateLookup() GenerateFromAlternate() ... C++ Class HTML display WriteHTML() MIFmemorycontents WriteVHDL() COE memorycontents EDIFnetlists XILINX Core Generator Load() XCO DPM RAM definition VHDLsimulationmodels Save() MakeSubClass() .cc, .heasyaccess LUT master file VHDL wrapper complete description of LUT: I/O definition, list of instances default contents (for each incarnation) Behavioral Simulation FPGA Synthesis & Implementation

  6. Generic Handling of GMT Look-Up-TablesLUT generation - Use in ORCA - Generation of files for firmware LUT Generation Appl. ORCA L1MuGMTLUT inputs, outputs, instances, contents Load(), Save() virtual AlternateLookup() GenerateFromAlternate() ... Lookup() L1MuGMTLUT inputs, outputs, instances, contents Load(), Save() virtual AlternateLookup() GenerateFromAlternate() ... child class L1MuGMT_XY_LUT inputs, outputs, instances, contents Load(), Save() virtual AlternateLookup() GenerateFromAlternate() ... Save() (2) ORCA simulationto be implemented … LUT master file Load() COE memorycontents WriteVHDL() Load() (One for each type of LUT in the GMT) 1. Derive a C++ child class 2. Implement LUT functionality in derived AlternativeLookup() 3. Call GenerateFromAlternative() 4. Call Save() LUT2HW tool L1MuGMTLUT inputs, outputs, instances, contents Load(), Save() virtual AlternateLookup() GenerateFromAlternate() ... XCO DPM RAM definition VHDL wrapper (3) Batch generationof files for Xilinx firmware (1) Lookup-table generation

  7. Cross-check of ORCA simulation with FPGA firmware & GMT board Single type of hardware test file for all chips and for GMT board All GMT inputs & outputs Intermediate results at various points in GMT For easier debugging: human readable with automatically generated comments such as parameters in meaningful units So far tested MIP and ISO assignment FPGA (barrel) with several hundred single-muon events Full agreement with ORCA Firmware Test: Data Flow ORCA hits digi DT GMT CSC GT RPC Calo GMTInputs intermediateresults GMTOutputs HW Testfile (ASCII) VHDL test bench(for single chip or entire GMT) Intermediate signals Chip or entire GMTVHDL Behavioral / Gate Level Output signals stimuli

  8. MIP and ISO Assignment FPGAs Xilinx XC2V3000 • Chip Inputs/Outputs • 8 muons 200 • 180 MIP/ISO bits 180 • out (isISO, isMIP) 16 • VME 36 • total 432 • Memories 18 kbit blocks • 96 / 96 used GMT Logic Board

  9. MIP and ISO Assignment FPGAsdevelopment of firmware • Developed VHDL model • Simulated behavioral model & cross-checked with ORCA • Synthesized using Synplify 7.21 • Implemented with Xilinx ISE 5.2 • Simulated chip-level VHDL &cross-checked with ORCA • Pin assignment to be re-iteratedwhen board is being routed Xilinx XC2V3000

  10. Improvements of GMT algorithm New additional overlap region cancel-out-units Optimized merging of pT measurements Development of tools Software for generation of look-up-table contents Software for handling of look-up-table and generation of HW files Generation of test data from ORCA simulation VHDL test bench Development of FPGA firmware MIP and ISO assignment chip (barrel) done & verified against ORCA Progress towards milestones as planned Conclusions on Global Muon Trigger

  11. Global Trigger PSB (Pipeline Synchronizing Buffer) Input synchronization (7 boards including GMT) GTL (Global Trigger Logic) Logic calculation (1-2 boards) FDL (Final Decision Logic) L1A decision (1 board) TCS (Trigger Control System Modeule) Central Trigger Control (1 board) L1A (Level-1 Accept Module) Delivery of L1A (1 board) TIM (Timing Board) Timing (1 board) GTFE (Global Trigger Frontend) Readout (1 board)

  12. VME interface VME to GTL6U +1.5V supply 80MHzGTL+ signals Channel Link signals ChannelLinkRec CONV chips GT Conversion Board GTL-CONV is used only in the Prototype Crate

  13. Crate for Prototype Global Trigger VME interface GTL_CONV PSB PSB GTL6U

  14. GTL-6U Prototype (right side) VME COND chips 4 muons 4x4 calo objects GTL+ signals Calculates 64 Trigger algorithms REC chips

  15. XC2V2000-4FF896C 50 Ohm connectors bottom side top side BGA: 1mm pitch, track width=83 mm Mezzanine Board (MEZZ896) MEZZ896 will be used in TCS-9U and FDL-9U

  16. Layout of USC55 Counting Room Racks Lower Floor

  17. GT Rack

  18. Boards and Cables in GT 9U Crate

  19. Global Trigger Status and Milestones May 2003 Milestones as of Nov. 2002 or updated • Custom Backplane for VME 9U crate • 6U Prototype: Channel Links ...existsMS 03/02 • 9U Backplane: 80MHz GTLp and Channel Links, ...design in progress MS 03/03 09/03 • PSB Input board (synchronisation, monitoring) • 6 channel 6U Prototype: Channel Link receivers... board tested MS 03/02 • 12 channel board: memories inside FPGAs ...conceptual designMS 06/04 • GTL Logic board: • Conversion board for prototype ... board tested MS 03/02 • GTL-6U prototype: 20 channels …board largely testedMS 06/03 • Signal transfer tested with test patterns -> ok • XDAQ compatible test program in C++ exists • Loading of conditions not tested yet (software under development) • GTL-9U board: 32 channels ...conceptual designMS 11/04 • 4, 4 isol. e/, 4e/, 4 central jets, 4 fwd jets, 4 t-jets, SET, ET mis, HT, 12 jet counts • TIM Timing board… New: board produced, tests in progessMS 06/03 • 6U size, TTCrx, clock and L1A distribution, also used by DTTF • FDL-9U Final Decision board... design in progress MS 06/03 11/03 • TCS-9U Central Trigger Control board... design in progress MS 04/03 09/03 • GTFE-9U Readout board...conceptual design MS 12/03 03/04

  20. Global Muon Trigger FPGA design  12/03 Global Trigger PROTOTYPE BACK-6U ok PSB-6U ok GTL-CONV ok GTL-6U Milestone 6/03 TIM-6U Milestone 6/03 Board production  06/04 GMT system tests  01/05 Chain Test with GCT (July 2003) Production, Full Chain and Slice Tests, Integration Global Trigger GTL-6U  produced, testing TIM-6U  produced, testing TCS-9U  09/03 BACK-9U  09/03 FDL-9U  11/03 GTFE  03/04 PSB-9U  06/04 System test (full chain) of 20-channel GT  06/04 Integration of GT/GMT with DAQ 01/06 Slice tests performed in Vienna as boards become available. Installation and commissioning in USC55 planned in phase with other subsystems (GCT, regional muon trigger systems) during second half of 2005. GTL-9U  11/04 GT system tests  6/05

  21. GT and GMT Manpower • Physicists • A. Taurok (Project engineer), C.-E. Wulz (GT coordinator) • H. Sakulin (logic and hardware design of GMT, simulation, on-line software) • J. Strauss (on-line software) • A. Jeitler (40%), P. Porth (60%), H. Rohringer (simulation) • N. Neumeister (simulation, mainly working in PRS) • Technicians (shared with DTTF) • H. Bergauer (60%), M. Padrta, K. Kastner - in Vienna • Ch. Deldicque - at CERN • Students • S. Kostner (20%), new: B. Neuherz (50%) (on-line software, hardware) • New: A. Nentchev (50%) (on-line software)

  22. Boards PSB-6U, BACK-6U, GTL-6U, GTL-CONV, TIM exist TCS-9U, FDL-9U are being finalized GTFE, GTL-9U foreseen in 2004, L1A depends on TTCci Software production XDAQ compatible software under development CVI-based set-up program being changed to C++ Integration with calorimeter trigger to be tested soon July 2003 Conclusions on Global Trigger

  23. This talk can be found at: • http://wwwhephy.oeaw.ac.at/p3w/cms/trigger/globalTrigger/trans/ • wulz_CPT_may2003.ppt • The GMT part of this talk can be found at: • http://wwwhephy.oeaw.ac.at/p3w/cms/trigger/globalMuonTrigger/trans/GMT-CPTWeek5May2003.pdf • Detailed information about the Global Trigger and the Global Muon Trigger is • available on the HEPHY Vienna web sites: • http://wwwhephy.oeaw.ac.at/p3w/cms/trigger/globalTrigger • http://wwwhephy.oeaw.ac.at/p3w/cms/trigger/globalMuonTrigger URL’s

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