1 / 8

Generating the Trace Qualification Configuration for MCDS from a High Level Language

Generating the Trace Qualification Configuration for MCDS from a High Level Language. Jens Braunes and Rainer G. Spallek. Objective. Create an interface to configure trace and debug tasks for MCDS (Multi-Core Debug Solution) Challenges: Multiple trace sources – one single trace stream

rylee-hubbard
Download Presentation

Generating the Trace Qualification Configuration for MCDS from a High Level Language

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Generating the Trace Qualification Configuration for MCDS from a High Level Language Jens Braunes and Rainer G. Spallek Design, Automation & Test in Europe, 2009

  2. Objective Design, Automation & Test in Europe, 2009 • Create an interface to configure trace and debug tasks for MCDS (Multi-Core Debug Solution) • Challenges: • Multiple trace sources – one single trace stream • Multi-Core / multi-bus  requires cross triggering • Powerful but complex trace qualification and trigger logic • Approach: • High level language and compiler for trace qualification • Provides overall system view – no separation between trace sources • Supports state machines to define complex but manageable analysis tasks

  3. Multi-Core Debug Solution (MCDS) • Configurable and scalable trigger,trace qualification, and tracecompression IP block (by Infineon) • For multi-core / multi-bus SoCs • Simultaneous recording of multiple trace sources – one single, time aligned trace stream • On-chip trace memory to overcome trace port bottleneck • Record only relevant data  complex trace qualification and trigger logic OCP-IP debug specification favors MCDS as implementation of a standardized debug environment within OCP-IP compliant SoCs. Design, Automation & Test in Europe, 2009

  4. High Level Language for Trace Qulification Design, Automation & Test in Europe, 2009 Quite similar to high level programming languages Statements to initiate debug and trace actions(e.g. enabling trace recording, generating core events, break targets, …) if-else to enable actions based on conditions Statements to build state machines(state labels, goto).

  5. Compiling Configuration Data forMCDS Trace Qualification • Resource allocation Design, Automation & Test in Europe, 2009 Transforming state machines into combinatorial logic Structure of trace qualification logic requires further transformations and simplification Routing of cross triggers between OBs

  6. Example and Case Study • Multi-core interaction: Two tasks, each executed by a separate processor core, are communicating via a shared memory location. This communication should be observed. TPC.PCcore1 pc1; TPC.PCcore2 pc2; TSignal Enter = pc1 == 0xD400049A; TSignal Leave = pc2 == 0xD40005BC; TPC.BusAddraddr; SharedMem = addr == 0xF0050040; // Write to bus from any busmaster: TData.BusAccess access; MemWrite = 0x200<=(access & 0x20e)<=0x20F; TData.BusData data; // State machine state0: if (Enter) then goto state0; state1: store pc1; store pc2; emitmcx.tick_enable; if (MemWrite and SharedMem) then trigger; storeaddr; store data; if (Leave) then goto state0; Design, Automation & Test in Europe, 2009

  7. Example and Case Study (2) 1 From trigger pools of all used OBs. 2 Two processor observation blocks, one bus observation block and MCX. 3 Two counters representing the states. 4 Adds one additional condition each. 5 Cross triggers used by 13 action conditions. Design, Automation & Test in Europe, 2009

  8. Thank You Jens Braunes plsProgrammierbare Logik &Systeme GmbHTechnologiepark02991 LautaGermany jens.braunes@pls-mc.comwww.pls-mc.com Rainer G. Spallek TechnischeUniversität DresdenDepartment of Computer ScienceInstitute of Computer Engineering01062 DresdenGermany rainer.spallek@tu-dresden.deweb.inf.tu-dresden.de/TeI/EDA Design, Automation & Test in Europe, 2009

More Related