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Explicit Gate Delay Model for Timing Evaluation

Explicit Gate Delay Model for Timing Evaluation. Muzhou Shao : University of Texas at Austin D.F.Wong : U. of Illinois at Urbana- Champaign Huijing Cao : Motorola, Inc. Youxin Gao : Synopsys, Inc., Li-Pen Yuan : Synopsys, Inc.,

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Explicit Gate Delay Model for Timing Evaluation

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  1. Explicit Gate Delay Model for Timing Evaluation Muzhou Shao : University of Texas at Austin D.F.Wong : U. of Illinois at Urbana-Champaign Huijing Cao : Motorola, Inc. Youxin Gao : Synopsys, Inc., Li-Pen Yuan : Synopsys, Inc., Li-Da Huang : University of Texas at Austin Seokjin Lee : University of Texas at Austin

  2. Value of Gate Modeling • One part of stage delay • Crucial in timing synthesis/optimization

  3. Previous Gate Delay Model • Switch-resistor model • k-factor functions • Lookup table model

  4. Previous Gate Delay Model–cont. • k-factor functions • Delay/transition are functions of input signal and gate load. • Lookup table model • Delay/transition is tabulated for each input, load pair.

  5. Previous Gate Delay Model–cont. • Switch-resistor model • Structure: • step voltage source • linear driver resistance • Advantages: • Simple • Stage delay

  6. Trends in DSM • The increasing of resistive shielding of interconnect. • The output impedance of gate reduces relatively.

  7. Trends in DSM –cont. • Step input --> piecewise • C_eff is needed in gate modeling.

  8. Our New Approach • Gate modeling work independent of its load. • Can be easily integrated into timing analysis. • Concise circuit structure.

  9. Structure of Explicit Gate Model Based on a second-order circuit.

  10. Parameters of Gate Model • Totally 5 unknown parameters • 4 unknown parameters in the model circuit. • R1 ,R2,C1,C2 • 1 unknown parameters in the input signal. • 

  11. Parameters of Gate Model –cont. • With two operating points, two poles are obtained.

  12. Parameters of Gate Model –cont. • Another two operating points, another two poles.

  13. Parameters of Gate Model –cont.

  14. Obtain Operating Points • There are four operating points of the gate output needed in the deduction. • Run SPICE twice to obtain the two groups of • (vi, ti). • Obtained from k-factor functions

  15. Another Parameter • The gate intrinsic delay and signal regenerating ability. •  is defined as tp  tr .

  16. Another Parameter –cont.

  17. Another Parameter –cont. • Choose an operating point of 50% power supply as (50%VDD, t50%).

  18. Two Ways to Set up the Model • Solving nonlinear equations. • “optimize” function of transit analysis in HSPICE.

  19. Focus of the Experimental Results • Can be pre-computed. • The saving of runtime is obvious. • The accuracy issue is focused on.

  20. Experimental Results • 36 gates of different types and technologies. • The gate load is randomly generated. • The input signal is also randomly chosen. • 3,600 experimental results all together. • MOS transistor model level is from 13 to 49.

  21. Experimental Results–cont. • Statistic results of computation errors in gate delay model.

  22. Waveform Comparisons (Driving Pin) Waveforms obtained from HSPICE simulations

  23. Waveform Comparisons (Sink Pin) Waveforms obtained at the fan-out point.

  24. Another Test Case • The test results on the clock tree of a commercial IC .

  25. Conclusion • Independent of gate load. • Can be pre-characterized. • No effective capacitance iteration. • Compatible with interconnect timing analysis.

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