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Serial Peripheral Interface (SPI)

Serial Peripheral Interface (SPI). Data Frame Format. Data frame format : Programmable data frame size : 8- bit 16-bit Programmable data order with MSB-first LSB-first. Master. SCK. MISO. MOSI. NSS. SPI Features (1/2).

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Serial Peripheral Interface (SPI)

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  1. Serial Peripheral Interface (SPI)

  2. Data Frame Format • Data frame format : • Programmable data frame size : • 8- bit • 16-bit • Programmable data order with • MSB-first • LSB-first Master SCK MISO MOSI NSS

  3. SPI Features (1/2) • Two SPIs: SPI1 on high speed APB2 and SPI2 on low speed APB1 • Full duplex synchronous transfers on 3 lines • Simplex synchronous transfers on 2 lines with or without a bi-directional data line • Programmable data frame size :8- or 16-bit transfer frame format selection • Programmable data order with MSB-first or LSB-first shifting • Master or slave operation • Programmable bit rate: up to 18 MHz in Master/Slave mode • NSS management by hardware or software for both master and slave:

  4. SPI Features (2/2) • Programmable clock polarity and phase • Dedicated transmission and reception flags (Tx buffer Empty and Rx buffer Not Empty) with interrupt capability • SPI bus busy status flag • Hardware CRC feature for reliable communication • Support for DMA Tx and Rx requests • Each SPI has a DMA Tx and Rx requests

  5. VDD Communication types • Full Duplex Communication : Slave Master SCK SCK MISO MISO MOSI MOSI NSS NSS Full Duplex • Simplex Communication : Slave Master SCK SCK MISO MISO MOSI MOSI VDD NSS NSS RxOnly(Slave)

  6. Software NSS Slave Slave MOSI SCK NSS MISO MOSI SCK NSS MISO VDD MOSI SCK NSS MISO MOSI SCK NSS MISO Master Master NSS Hardware & Software Management Hardware NSS • Both Master and Slave NSS pins could be used for other purpose • Provides the possibility of dynamic change of Master/Slave operations: No hardware limitation to switch from master to slave or slave to master in the same application

  7. CRC Calculation • Example of n data transfer between two SPIs followed by the CRC transmission of each one in Full-duplex mode Taken from SPI1 TXCRC register and sent to SPI2 MOSI Data 1 Data 2 … Data n CRC[1..n] Taken from SPI2 TXCRC register and sent to SPI1 MISO Data’ 1 Data’ 2 … Data’ n CRC’[1..n] SCK

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