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CS 140 Lecture 13 Combinational Standard Modules. Professor CK Cheng CSE Dept. UC San Diego. Part III. Standard Modules. Interconnect Modules: 1. Decoder, 2. Encoder 3. Multiplexer, 4. Demultiplexer. Multiplexer. Definition Logic Diagram Application. En. D 2 n -1 -D 0. y.
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CS 140 Lecture 13Combinational Standard Modules Professor CK Cheng CSE Dept. UC San Diego
Part III. Standard Modules Interconnect Modules: 1. Decoder, 2. Encoder 3. Multiplexer, 4. Demultiplexer
Multiplexer • Definition • Logic Diagram • Application
En D2n-1-D0 y (Data input) Sn-1,0 (Control input) 3. Mux (Multiplexer): Definition Description If En = 1 y = Di where i = (Sn-1, .. , S0) Else y = 0
Multiplexer (Mux): Definition • Selects between one of N inputs to connect to the output. • log2N-bit select input – control input • Example: 2:1 Mux
Multiplexer Definition: Example En If D0 = 0 and S1S0 = 00 => y = 0 If D0 = 1 and S1S0 = 00 => y = 1 D0 0 D1 1 y D2 2 D3 3 S1 S0
Multiplexer: Logic Diagram • Tristates • For an N-input mux, use N tristates • Turn on exactly one to select the appropriate input • Logic gates • Sum-of-products form
Multiplexer Application • Mux for a Boolean function with truth table as input
Multiplexer Application: universal set {Mux} Example 1: Given f (a,b,c) = Sm (0,1,7) + Sd(2), implement with an 8-input Mux. En Id a b c f 0 0 0 0 1 1 0 0 1 1 2 0 1 0 - 3 0 1 1 0 4 1 0 0 0 5 1 0 1 0 6 1 1 0 0 7 1 1 1 1 1 0 1 2 3 4 5 6 7 1 0 0 y 0 0 0 1 S0 S1 S2 a b c
En 1 0 0 1 y 0 2 c 3 S1 S0 a b Multiplexer Application Example 2: Given f (a,b,c) = Sm (0,1,7) + Sd(2), implement with 4-input Muxes. D (c) D0 (c) =1 D1 (c) =0 D2 (c) =0 D3 (c) =c a 0 0 1 1 b 0 1 0 1 c = 0 1 - 0 0 c = 1 1 0 0 1
Multiplexer Application Example 3: Given f (a,b,c) = Sm (0,1,7) + Sd(2), implement with 2-input Muxes. En b’ En 0 y 0 1 0 c 1 a b a 0 1 00 01 10 11 1 1 - 0 0 0 0 1 D (b,c) D0 (b,c) D1 (b,c) D0 (b,c) = b’ D1 (b,c) = bc • - • 1 0 0 0 0 1 c c b b D1 (b,c) b 0 1 c = 0 0 0 c = 1 0 1 l1(0) = 0 l1(c) = c
4. Demultiplexers En yi = x if i = (Sn-1, .. , S0) & En = 1 yi = 0 otherwise y2n-1 -y0 x S(n-1,0) Control Input
xn xn-1 x0 x-1 s s / n En d l / r y0 yn-1 xi-1 xi+1 xi s 3 2 1 0 1 En d 0 yi Shifter yi = xi-1 if En = 1, s = 1, and d = L = xi+1 if En = 1, s = 1, and d = R = xi if En = 1, s = 0 = 0 if En = 0 Can be implemented with a mux
Barrel Shifter shift x 0 1 0 1 0 1 O or 1 shift s0 O or 2 shift s1 0 1 0 1 0 1 0 1 0 1 O or 4 shift s2 0 1 0 1 0 1 0 1 y 0 1 0 1