Very Large Scale Integration II - VLSI II Synthesis Using RTL Compiler Hayri U ğur UYANIK

1. Very Large Scale Integration II - VLSI II Synthesis Using RTL Compiler Hayri Uğur UYANIK ITU VLSI Laboratories Istanbul Technical University

2. Synthesis Using RTL Compiler CNT_16 Module: 16 bit up counter with asynchronous active-low reset `timescale 1ns/1ps module CNT_16(CLK, RSTB, OUT); input CLK, RSTB; output [15:0] OUT; reg [15:0] OUT; always@(posedge CLK or negedge RSTB) begin if(!RSTB) begin OUT <= 0; end elsebegin OUT <= OUT + 1; end end endmodule

3. Synthesis Using RTL Compiler CMP_16 Module: Comparator which compares the 16 bit input with 50. `timescale 1ns/1ps module CMP_16(IN, OUT); input [15:0] IN; output OUT; reg OUT; always@(IN) begin if(IN <= 50) begin OUT = 0; end elsebegin OUT = 1; end end endmodule

4. Synthesis Using RTL Compiler TOP Module: The top module which connects both. The resulting design makes OUT=1 after 50 clock cycles. `timescale 1ns/1ps module TOP(CLK, RSTB, OUT); input CLK, RSTB; output OUT; wire [15:0] OUT_16; CMP_16 U1(OUT_16, OUT); CNT_16 U2(CLK, RSTB, OUT_16); endmodule

5. Synthesis Using RTL Compiler Make a new folder

6. Synthesis Using RTL Compiler Copy all Verilog files to newly created folder

7. Synthesis Using RTL Compiler rc –gui

8. Synthesis Using RTL Compiler RTL Compiler windows

9. Synthesis Using RTL Compiler set_attribute lib_search_path /work/kits/ams/3.70/liberty/c35_3.3V

10. Synthesis Using RTL Compiler set_attribute library {c35_CORELIB.lib}

11. Synthesis Using RTL Compiler read_hdl CNT_16.v read_hdl CMP_16.v read_hdl TOP.v

12. Synthesis Using RTL Compiler elaborate TOP

13. Synthesis Using RTL Compiler Sub Blocks

14. Synthesis Using RTL Compiler Technology independent D type Flip Flop

15. Synthesis Using RTL Compiler Technology independent adder

16. Synthesis Using RTL Compiler define_clock -period 100000 -fall 80 -rise 80 -name clkin /designs/TOP/ports_in/CLK

17. Synthesis Using RTL Compiler set_attribute slew {100 100 200 200} [find -clock clkin]

18. Synthesis Using RTL Compiler external_delay -input 1000 -clock [find -clock clkin] -edge_rise [find /des* -port ports_in/*]

19. Synthesis Using RTL Compiler external_delay -output 1000 -clock [find -clock clkin] –edge_rise /designs/TOP/ports_out/*

20. Synthesis Using RTL Compiler synthesize -to_mapped

21. Synthesis Using RTL Compiler Technology dependent D type Flip Flop

22. Synthesis Using RTL Compiler Technology dependent adder

23. Synthesis Using RTL Compiler write –mapped > TOP_syn.v

24. Synthesis Using RTL Compiler write_sdc > TOP.sdc

25. Synthesis Using RTL Compiler report_timing >timing_report.txt

26. Synthesis Using RTL Compiler report_area >area_report.txt

27. Synthesis Using RTL Compiler bgx_shell

28. Synthesis Using RTL Compiler BuildGates

29. Synthesis Using RTL Compiler source /work/kits/ams/3.70/buildgates/c35_3.3V/read_libs.tcl

30. Synthesis Using RTL Compiler read_verilog -st TOP_syn.v

31. Synthesis Using RTL Compiler write_sdf -prec 3 -edges check_edge -splitsetuphold -splitrecrem -remashold -force_calculation TOP.sdf

32. Synthesis Using RTL Compiler New Testbench: `timescale 1ns/1ps `include "/work/kits/ams/3.70/verilog/c35b4/c35_CORELIB.v" `include "/work/kits/ams/3.70/verilog/udp.v“ module TEST_TOP; reg CLK, RSTB; wire OUT; initial $sdf_annotate("TOP.sdf",U1); initialbegin RSTB = 0; CLK = 0; #30 RSTB = 1; #100000 $finish; end always #50 CLK = ~CLK; TOP U1(CLK, RSTB, OUT); endmodule

33. Synthesis Using RTL Compiler Add `timescale 1ns/1ps to TOP_syn.v and simulate OUT rises 1.225nsafter the rising edge of CLK