A Low-Energy Reconfigurable Fabric For Embedded Computing

1. A Low-Energy Reconfigurable Fabric For Embedded Computing Gayatri Mehta, Justin Stander, Colin Ihrig, Mustafa Baz, Brady Hunsaker and Alex K. Jones Department of Electrical & Computer Engineering, University of Pittsburgh Motivation SuperCISC Architecture Mapping of a benchmark onto the fabric • FPGAs exhibit poor power characteristics compared to ASICs making them less desirable for mobile and battery-powered applications. • ASICs exhibit better power characteristics but no programmability. Solution: Reprogrammable, Low-Energy Fabric The energy of 5:1 multiplexer fabric is • within 5-10X of the ASIC implementation • 10X better than the Virtex II Pro FPGA • 100X better than the Intel Xscale Processor at 733 MHz Mapping techniques used to map a benchmark onto fabric: -Heuristic Mapping -Mixed-Integer Linear Programming -Constraint Programming -Simulated Annealing Micro-Power Fabric Model Automated mapping onto the fabric System-Level Interconnect Study temp1 = x* y; temp2 = z*temp1; if (temp2 < 255) result1 = temp2<<16 ; else result1 = temp1; result1 += (((temp1)>>16)-0xffff); Fabric is comprised of power-optimized ALUs and multiplexer-based interconnect It mimics the computational style of SDFGs FPGA-like programmable ASIC-like power characteristics 4:1 multiplexer interconnect 5:1 multiplexer interconnect A representative Graph from signal processing applications Energy Consumption Results Embedding the representative graph into different interconnects 5:1 interconnect 4:1 interconnect Energy comparison of different interconnect patterns Energy comparison of different hardware and software implementations 355:1 interconnect 3553:1 interconnect