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Spr 2011 ECE 111 SHA-1 Final Project

Spr 2011 ECE 111 SHA-1 Final Project. Team members: Alice Doe, alice.doe@ucsd.edu Bob Doe, john.doe@ucsd.edu Part 1: Min Delay Part 2: Min Delay*Area. Part 1: State Machine. Put state machine here. Part 1: Summary. Lines of Verilog Code: e.g. 300

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Spr 2011 ECE 111 SHA-1 Final Project

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  1. Spr 2011 ECE 111 SHA-1 Final Project • Team members: • Alice Doe, alice.doe@ucsd.edu • Bob Doe, john.doe@ucsd.edu • Part 1: Min Delay • Part 2: Min Delay*Area

  2. Part 1: State Machine • Put state machine here

  3. Part 1: Summary • Lines of Verilog Code: e.g. 300 • Clock period: in nanoseconds, e.g. 9.00 ns. • Clock cycles: for v6/120 bytes, e.g. 300 • Delay: in microseconds, e.g. 2.70 us • ALUTs: e.g. 1000 • Registers: e.g. 1000 • Area: ALUTs+ Registers, e.g. 2000 • Delay * Area: e.g. 0.00540

  4. Part 1: Cycles Breakdown • Total cycles = e.g. 300 cycles • Initialization = e.g. 2 cycles • Cycles per block = e.g. 99 cycles • Initialization per block = 2 cycles • 80 cycles + 16 cycles = 96 cycles per block • Each round, read, compute, or pad w[i] • If w[0]…w[15], add a dummy wait state • Updating 80 rounds of hash = 80 cycles • Post-processing per block = 1 cycle • (each of your cycle may combine many steps) • Post-processing = e.g. 1 cycle

  5. Part 1: Continue • Please add anything else noteworthy in your design • e.g., what you tried to pipeline, what you tried to reduce the clock period, …

  6. Part 2: State Machine • Put state machine here

  7. Part 2: Summary • Lines of Verilog Code: e.g. 400 • Clock period: in nanoseconds, e.g. 5.00 ns. • Clock cycles: for v6/120 bytes, e.g. 585 • Delay: in microseconds, e.g. 2.925 us • ALUTs: e.g. 700 • Registers: e.g. 966 • Area: ALUTs+ Registers, e.g. 1666 • Delay * Area: e.g. 0.00487

  8. Part 2: Cycles Breakdown • Total cycles = e.g. 585 cycles • Initialization = e.g. 2 cycles • Cycles per block = e.g. 194 cycles • Initialization per block = 1 cycle • Reading/padding in 16 words w[0] … w[15] = 32 cycles • Computing w[17] … w[69] = 80 cycles • Updating 80 rounds of hash = 80 cycles • Post-processing per block = 1 cycle • (each of your cycle may combine many steps) • Post-processing = e.g. 1 cycle

  9. Part 2: Continue • Please add anything else noteworthy in your design • e.g., how you minimized area …

  10. Notes • The previous slides just provide example numbers. • They are NOT meant to be representative numbers for your designs. • Your designs may have bigger or smaller numbers. Just report what your designs can achieve.

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