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Statistical Leakage and Timing Optimization for Submicron Process Variation

Statistical Leakage and Timing Optimization for Submicron Process Variation. Yuanlin Lu and Vishwani D. Agrawal ECE Dept. Auburn University Auburn, AL 36849, USA 20 th International Conference on VLSI Design Bangalore, January 9, 2006. Previous Work and Problem Statement.

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Statistical Leakage and Timing Optimization for Submicron Process Variation

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  1. Statistical Leakage and Timing Optimization for SubmicronProcess Variation Yuanlin Lu and Vishwani D. Agrawal ECE Dept. Auburn University Auburn, AL 36849, USA 20th International Conference on VLSI Design Bangalore, January 9, 2006 VLSI Design '07

  2. Previous Work and Problem Statement • Previous Work: Mixed integer linear program (MILP) for optimum Dual-Vth and delay buffer assignment for • Minimum leakage • Glitch elimination • Overall delay specification • Lu and Agrawal, “Leakage and Glitch Minimization for Power-Performance Tradeoff,” JOLPE, vol. 2, no. 3, pp. 1-10, December 2006. • Problem Statement: to minimize the leakage and glitch power (not included in this paper) considering process variation. • Overall nominal delay, process variability and statistical timing yield are specified. VLSI Design '07

  3. Motivation • Present trends in semiconductor technology: • Shrinking device dimensions. • Leakage power is a dominant contributor to the total power consumption. • Large variations in process parameters can cause a significant increase in leakage current because of an exponential relation between the leakage current and some key process parameters. VLSI Design '07

  4. Effects of Process Variation on Leakage and Performance S. Borkar, et al., Parameter variations and impact on circuits and microarchitecture, DAC 2003. too leaky too slow • 0.18µ CMOS process • 20X leakage variation • 30% clock frequency variation • low leakage chips with too low frequency must be discarded • high frequency chips with too high leakage must also be discarded VLSI Design '07

  5. Leakage in C432 Due to Global Process Variation (3σ = 15%, Spice simulation) • Subthreshold is most sensitive to the variation in the effective gate length. VLSI Design '07

  6. Leakage in C432 Due to Local Process Variation (3σ = 15%) • Subthreshold is most sensitive to the variation in the effective gate length. VLSI Design '07

  7. Leakage Distribution of C432 Due to the Variation of Leffand Vth(3σ =15%) • Global variation has a stronger effect on the leakage distribution. VLSI Design '07

  8. Comparison of Leakage Distribution of C432 Due to Process Parameter Variations VLSI Design '07

  9. Statistical Leakage Modeling R. Rao, et al. “Parametric Yield Estimation Considering Leakage Variability,” DAC 2004. VLSI Design '07

  10. Statistical Delay Modeling Statistical – normal distribution Deterministic Let Mean Standard Deviation A. Davoodi and A. Srivastava, “Probabilistic Dual-Vth Optimization Under Variability,” Proc.ISLPED, 2005. VLSI Design '07

  11. MILP Formulation (Basic)(Deterministic vs. Statistical) Deterministic Approach Delay and subthreshold current of every gate are assumed to be fixed and without any effect of the process variation. Basic MILP Minimize the total leakage, keeping the circuit performance unchanged. Statistical Approach Treat delay, timing and leakage as random variables with normal distributions. Basic MILP Minimize the total nominal leakage, keeping a certain timing yield (η). Minimize" i Î gate number Subject to" k Î PO Minimize" i Î gate number Subject to" k Î PO VLSI Design '07

  12. Real Variables of MILP • Delay of gate i, Di , is a Gaussian random variable N(µDi , σDi) • Maximum signal arrival time at the output of gate i, Ti , is a Gaussian random variable N(µTi , σTi) • For gate i with input from gate j, Ti ≥ Tj+ Di , µTi ≥ µTj + µDi A linear approximation used for σTi VLSI Design '07

  13. Integer Variables of MILP • For gate i, Xi= [0, 1] • Ileakage, i = ILi Xi + IHi (1 – Xi) • Di = DLi Xi + DHi (1 – Xi) • Where ILi , IHi , DLi , and DHi are determined by Spice simulation of gate i VLSI Design '07

  14. Leakage Power Saving Due to Statistical Modeling with Different Timing Yields (η) VLSI Design '07

  15. Power-Delay Curves of Statistical and Deterministic Approaches for C432 • When performance is kept unchanged: • Leakage power reduced by deterministic approach normalized to 1 unit. • 0.65 unit and 0.59 unit leakage power achieved by statistical approach with 99% and 95% timing yields, respectively. • Lower the timing yield, higher is power saving. • With a further relaxed Tmax , all three curves will give more reduction in leakage power. VLSI Design '07

  16. Leakage Power Distribution with Different Timing Yields (η) VLSI Design '07

  17. Leakage Power Distribution of Optimized Dual-Vth C7552 VLSI Design '07

  18. Conclusion • A mixed integer linear programming method statistically minimizes leakage power and eliminates glitch power in a dual-Vth design under process variations. • Experimental results show 30% more leakage power reduction by this statistical approach compared with the deterministic approach. • Impacts of process variation on leakage power and circuit performance are simultaneously reduced when a small yield loss is allowed. VLSI Design '07

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