1 / 30

Gate Leakage Estimation and Minimization in Deep-Submicron CMOS Circuits

Gate Leakage Estimation and Minimization in Deep-Submicron CMOS Circuits. Rafik S. Guindi Nile University rguindi@ieee.org. Outline. What is Gate Leakage? Power Consumption in CMOS Structure dependence State dependence Applications Combinatorial circuits Sequential circuits.

masako
Download Presentation

Gate Leakage Estimation and Minimization in Deep-Submicron CMOS Circuits

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Gate Leakage Estimation and Minimization in Deep-Submicron CMOS Circuits Rafik S. Guindi Nile University rguindi@ieee.org

  2. Outline • What is Gate Leakage? • Power Consumption in CMOS • Structure dependence • State dependence • Applications • Combinatorial circuits • Sequential circuits EED 2008

  3. What is Gate Leakage? • Direct tunneling gate current components VG = VDD VS = 0 VD ~ 0 GATE source drain Tox OXIDE BULK channel LG Oxide thickness is getting smaller and smaller EED 2008

  4. JG Tox = 1.4 nm 102 A/cm2 Tox = 1.8 nm Tox = 2.0 nm 10-2 A/cm2 Tox = 2.5 nm VD = 0 V 10-6 A/cm2 10-10 A/cm2 VG 0 V 1 V 2 V EED 2008

  5. Main component: Dynamic power Power Consumption in CMOS Trend αVDD2 VDD (V) 3.3 2.5 1.8 1.2 1.0 Transistor scaling LG (nm) 90 60 45 32 22 αCL αfclk EED 2008

  6. Active mode Idle mode Active Idle (clock running) (clock fixed) Dynamic power Leakage EED 2008

  7. Power Consumption in CMOS Circuits: Dynamic powerLeakage power Subthreshold leakageGate leakage Main reason comes from a reduced Vt (Voltage scaling) Increases as the gate oxide gets thinner (transistor scaling) Power lost due to leakage is increasingly larger in a CMOS chip EED 2008

  8. Scaling Effect: Dynamic powerLeakage power Subthreshold leakageGate leakage • Tox = 1.7 nm  subthreshold • dominates • Tox = 1.5 nm  comparable • Tox = 1.3 nm  gate-current • dominates PROBLEM: Gate leakage will dominate in the future, as oxides get thinner SOLUTIONS: Process/technology  Circuit techniques EED 2008

  9. 0.709 0.402 1.267 0.152 0.554 1.976 5.626 6.774 6.973 0.837 7.611 12.599 3.804 3.720 0.076 0.634 4.438 3.796 18.848 21.314 1.522 12.677 22.836 31.525 2-input NOR 2-input NAND 2-input NAND 2-input NOR Sub Sub Gate Gate Total Total 13.548 11.252 1.267 0.152 13.700 12.519 7.037 6.460 6.339 0.761 7.221 13.376 10.657 9.424 0.837 6.973 16.397 11.494 0.695 1.487 12.677 1.522 2.217 14.164 Inverter Inverter Sub Sub Gate Gate Total Total 5.626 6.774 0.634 0.076 6.260 6.850 9.424 10.657 0.761 6.339 11.418 15.763 Tox = 1.7 nm Tox = 1.5 nm Sub Gate Total Sub Gate Total 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 1 EED 2008

  10. B B C A C A D D A B C D B C D A Structure Dependence • an ‘on’ transistor in a CMOS logic circuit may or may not leak depending on the circuit structure, and on the transistor’s place in it EED 2008

  11. IG Strong inversion 20 A/cm2 VGS = 1.2 V 0.1 A/cm2 Tox = 1.5 nm 1 mA/cm2 VGS = 0.6 V 10 mA/cm2 VDS Threshold EED 2008

  12. NMOS in strong inversion: • Gate leakage: High 0 V 0 V Vdd 0 V Vdd 0 V 0 V Vdd Vdd Vdd EED 2008

  13. NMOS at the threshold • Gate leakage: Negligible Vdd Vdd Vdd PMOS on PMOS on PMOS on Vdd Vdd Vdd Vdd Vdd Vdd- Vt Vdd- Vt Vdd Vdd- Vt Vdd Vdd Vdd- Vt Vdd- Vt EED 2008

  14. Logically equivalent structures: 1 1 1 off 1 1 1 EED 2008

  15. Stack effect: The higher up in the stack, the lower the chance that it would leak when on Always leaks when on EED 2008

  16. State Dependence • for a given structure the total gate leakage depends on the input state 0.1 0.1 0.1 0.1 0 0 0 1 1 0 1 1 1 1 1 Total: 0.2 1.1 0.1 2 EED 2008

  17. Normalized state-dependent gate current tables NAND NOR Unsized Sized Unsized Sized W = 1x W = 2x W = 1x W = 1x n n n n Input W = 1x W = 3x W = 1x W = 6x p p p p 0 0 0.2 0.6 0.2 1.2 0 1 1.1 2.3 1 1 1 0 0.1 0.3 1.1 1.6 1 1 2 4 2 2 EED 2008

  18. Applications • Estimation of total gate leakage in a combinatorial CMOS circuit: • Given probabilities of primary inputs, compute signal probabilities at all nodes • Compute the probability of each state (00, 01, 10, 11) for each gate • Use state-dependent gate current tables in conjunction with signal probabilities EED 2008

  19. A X B Z C Y D • Example: NAND1 NAND2 NAND3 PA = 0.7 PC = 0.5 PX = 0.51 PB = 0.7 PD = 0.1 PY = 0.95 I 0,0 = 0.6 P 0,0 0.09 0.45 0.0245 I 1,0 = 2.3 P 0,1 0.21 0.05 0.4655 I 1,0 = 0.3 P 1,0 0.21 0.45 0.0255 I 1,1 = 4 P 1,1 0.49 0.05 0.4845 Total leakage per gate 2.56 0.72 3.031 6.311 EED 2008

  20. Minimization of total gate leakage through pin assignment: • above example: • best case improvement of 23.6% over worst case NAND1 NAND2 NAND3 Total original connection 2.56 0.72 3.031 6.311 inputs interchanged 2.56 1.52 2.151 6.231 best case 2.56 0.72 2.151 5.431 worst case 2.56 1.52 3.031 7.111 EED 2008

  21. average best worst 22.76% 18.08% 14.33% c1355 (unsized) Reordered circuits Original interconnection average best worst 470 485 500 515 530 545 560 575 590 605 620 635 Total leakage EED 2008

  22. Worst-case leakage Actual average Best-case leakage Smallest B/W improvement Largest B/W improvement 6.1 3.1 8.6 257.9 230.2 312.7 588.6 483.0 642.7 466.1 405.0 530.6 621.1 475.6 701.4 1450.2 1293.0 1566.5 2257.3 2123.5 2368.1 12.7 6.8 17.6 451.0 397.1 557.8 1054.8 857.5 1144.7 772.6 651.4 891.4 1173.1 886.0 1326.5 2373.2 2052.6 2616.1 3603.9 3221.1 3903.6 Unsized c17 1.82% 55.75% c432 15.88% 22.76% c499 15.52% 22.43% c880 9.32% 18.44% c1355 20.82% 29.73% c2670 10.57% 16.76% c6288 2.58% 6.48% c17 1.76% 53.90% Sized c432 18.28% 26.31% c499 17.34% 24.59% c880 11.87% 23.02% c1355 21.99% 31.28% c2670 13.08% 20.63% c6288 4.98% 12.86% EED 2008

  23. Low-leakage standby state • especially in sequential circuits • dynamic power is reduced by holding the clock in parts of the circuit (standby mode) • it is important to hold the circuit in a low-leakage state EED 2008

  24. sleep sleep sleep sleep c1355 (unsized) Reordered circuits Original interconnection ‘running’ leakage 470 485 500 515 530 545 560 575 590 605 620 635 Total leakage EED 2008

  25. Total number of gates Gates with interchanged inputs Average leakage Leakage reduction Original circuit Alternate circuit Unsized c17 6.1 5.8 4.1% 6 1 c432 257.9 250.4 2.91% c499 588.6 526.5 10.55% 307 72 c880 604 194 466.1 443.5 4.84% c1355 658 321 621.1 526.2 15.28% 730 290 c2670 1952 542 1450.2 1370.6 5.49% c6288 2672 1260 2257.3 2242.2 0.67% Sized c17 6 1 12.7 12.2 3.94% c432 307 72 451.0 435.6 3.4% c499 730 289 1054.8 930.5 11.78% c880 604 194 772.6 724.1 6.28% c1355 658 321 1173.1 983.3 16.18% c2670 1952 542 2373.2 2212.3 6.78% c6288 2672 1260 3603.9 3513.4 2.51% EED 2008

  26. Sequential Circuits: • We consider State Assignments for Finite State Machines (FSMs) that minimize the power lost to Leakage in the Sequential part of the FSM EED 2008

  27. Estimation of gate leakage in flip-flops: (QCD) (QCD) EED 2008

  28. Example: A 4-State FSM EED 2008

  29. Assigning states for this FSM results in: S = {C0,C1,C2,C3} Calculating Cst for HLFF: Cst = P1,1*Leakage(s1,s1) + P1,2*Leakage(s1,s2) + P2,1*Leakage(s2,s1) + P2,3*Leakage(s2,s3) + P3,3*Leakage(s3,s3) + P3,4*Leakage(s3,s4) + P4,2*Leakage(s4,s2) + P4,3*Leakage(s4,s3) = 8+25.8+23.6+81.7+53.7+150.2+76.3+81.7 = 501 The equivalent assignments technique produces: S = {C2,C3,C0,C1} with Cst = 480 EED 2008

  30. MCNC Benchmark Circuits EED 2008

More Related