PCI Express Hard IP Quick Start Guide with SOPC Builder

1. PCI Express Hard IP Quick Start Guide with SOPC Builder

2. Objectives • Implement a PCI Express system from design to working model in under 45 minutes using an Arria® II GX* device & SOPC Builder • You will see • How easy it is to create PCI Express designs using Arria II GX device Hard IP blocks and transceivers • How SOPC Builder simplifies complex systems like PCI Express * Procedures presented may be similarly performed on Stratix IV GX devices

3. PCI Express Hard IP Quick Start Guide with SOPC Builder Altera PCI Express Solutions

4. Altera PCI Express Solutions • Arria II GX FPGAs • Arria II GX embedded transceivers • Arria II GX PCIe Hard IP blocks • SOPC Builder • PCI Express Compiler

5. Introducing Arria II GX FPGAs • Increased system integration on a low-cost FPGA • Up to 256k equivalent logic elements • Up to 8.5Mbits of on-chip RAM and 736 18x18 multipliers • Up to 16 full-duplex transceivers up to 3.75Gbps • Lower power • 40nm process with 0.9V core voltage • <100mW per transceiver channel (@ 3.125Gbps) • Transceiver FPGA design made easy • Built-in PCI Express hard IP • Single design environment • Protocol IP packs, design examples, and reference designs Low Power, Low Cost, Easy to Use

6. Arria II GX FPGA Architecture • DSP • 56to736multipliers • Logic • 16Kto256KLEs • Configurable I/O • Up to 612 I/O • 1-Gbps LVDS • 600-Mbps DDR2and DDR3 • Transceivers • Up to 3.75 Gbps • 4 to 16 channels • 100 mW per channel • Internal memory • 0.7 to 9 Mbits of block memory • Up to 5 Mbits of LAB memory • Hard PCI Express IP • Gen1.1 x1, x4, x8 Up to 6 PLLs

7. Transceiver Channel 3 Transceiver Channel 2 Transceiver Channel 1 Transceiver Channel 0 TX3 & RX3 TX2 & RX2 TX1 & RX1 TX0 & RX0 Transceiver Block Architecture • Easily configured using Quartus® II MegaWizard® plug-ins PIPE to FPGA PCIe Link Arria II GX device with 8 transceiver channels (2 transceiver blocks) Central Control Unit (CCU) Clock Management Unit 1 Clock Management Unit 0

8. Arria II GX FPGA PCI Express Hard IP Block Transaction Layer Data Link Layer PHYMAC Layer Embedded Transceiver Block Transceiver Block n Transceiver Block 2 PIPE Transceiver Block 1 Transceiver Block 0 To / from Slot or cable PCI Express Hard IP Block • Performs transaction, data link, and PHYMAC layer functionality • Supports • PCI Express Gen 1.1 • x1, x4 & x8 lane configurations • Root port and endpoint applications • Connects directly to embedded transceivers using internal PIPE interface • Shared by two adjacent transceiver blocks • Enabled through the PCI Express Compiler Wizard

9. PCI Express Hard IP Diagram • Configurable maximum payload size • 128, 256, or 512 bytes • 1 Virtual Channel • 4-Kbyte receive buffer • 2-Kbyte transmit retry buffer • 64-bit application datapath width • Interrupt support (legacy, MSI & MSI-X) • Advanced error reporting (AER) support • Power management support • Local management interface (LMI) to access configuration registers • Status & debug interface PLD Fabric Transceiver Block PCI Express Hard IP Block Application Layer PMA PCS Clock & Reset Selection PCI Express Protocol Stack Adapter TL Interface FPGA Interface PIPE Transceiver Block PMA PCS Local Mgmt IF (LMI) Retry Buffer VC RX Buffer

10. Example PCIe Hard IP Location

11. SOPC Builder • System design tool enabling designers to describe their system in design blocks • Automates IP Block connectivity • Supports both Memory-mapped and Streaming systems Reduce Development Time by Weeks!

12. PCI Express Compiler • Configures PCIe MegaCore® IP function • Includes all PCIe Hard IP settings • Includes embedded transceiver blocks • Output files • Verilog HDL or VHDL wrapper files • Tcl constraint file • SDC file for TimeQuest timing analysis • Application layer design example & testbench to verify chosen settings

13. PCI Express / SOPC Builder Design Flow • PCI Express Compiler gets called from SOPC Builder to configure PCIe MegaCore block and add to embedded system • Open SOPC Builder from the Quartus II software to build embedded system • SOPC Builder generates HDL that is added to Quartus II project for compilation into Arria II GX device

14. PCI Express Hard IP Quick Start Guide with SOPC Builder PCI Express Endpoint using SOPC Builder Demonstration

15. Memory DMA DMA DMA Example PCIe-SOPC Builder System

16. PCIe Endpoint Design Example

17. Design Example Simulation • Modelsim™ simulation directory generated at <sopc_builder_system>_sim • Scripts to simplify setting up & running ModelSim • Testbench files located in directory <pcie_component_name>_examples • Uses an auto-generated bus functional model (BFM) to emulate the other end of the PCIe link • Performs link initialization and generates verification messages • Modify files altpcietb_bfm_driver.v or .vhd to perform additional transactions

18. PCI Express Compiler / SOPC Builder Demonstration Click here if demo does not open

19. PCI Express Hard IP Quick Start Guide with SOPC Builder Summary

20. Summary • SOPC Builder makes designing complex PCI Express systems straightforward and simple • Arria II GX Hard IP block provides a low-cost and easy-to-use way to implement your PCI Express solution

21. Additional Materials • Arria II GX FPGA Overview • Arria II GX Getting Started • Arria II GX Design Resources • Altera PCI Express Solutions webpage • Altera PCI Express Hard IP webpage • Altera Online training • PCI Express online training for Altera 40 nm devices • Using SOPC Builder • Altera Documentation • Arria II GX Device Handbook • PCI Express Compiler User Guide • PCI Express protocol resources • Download PCIe Specification at PCI-SIG (www.pcisig.com) • Training and reference materials available from Mindshare Inc. (www.mindshare.com)

22. Your Feedback is important • For any feedback or questions regarding this training, please send an e-mail to certfae@altera.com