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This paper discusses the concept of variable-time-frame gate-level abstraction and its benefits in improving bounded model checking (BMC) and interpolation-based model checking. The proposed approach automatically adds logic to time-frames on demand, reducing the size of the SAT solver and improving scalability. Experimental results show significant improvements in proving problem unsatisfiability and reducing solver runtime.
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Variable-Time-Frame Gate-Level Abstraction Alan Mishchenko Niklas Een Robert Brayton UC Berkeley Jason Baumgartner Hari Mony Pradeep Nalla IBM
Overview • Introduction • Motivation • Algorithm • Experimental results • Conclusion
Abstraction • Finding a subset of logic gates of the miter, large enough to complete the proof
Taxonomy of Abstraction Methods • Automatic vs. manual • SAT-based vs. BDD-based vs. other • Proof-based vs. CEX-based vs. hybrid • Flop-level vs. gate-level • Fixed time-frame vs. variable time-frame
The Proposed Approach is… • Automatic • SAT-based • Hybrid • Gate-level • Variable time-frame
Previous Work Flop-level abstraction N. Een, A. Mishchenko, and N. Amla, "A single-instance incremental SAT formulation of proof- and counterexample-based abstraction", Proc. FMCAD'10. Gate-level abstraction J. Baumgartner and H. Mony, “Maximal Input Reduction of Sequential Netlists via Synergistic Reparameterization and Localization Strategies”. Proc. CHARME’05, pp. 222-237. 6
Motivation • Flop-level abstraction is too crude • Adds too much logic to the abstracted model (but refinement with external CEXes is easier…) • Gate-level abstraction is also too crude • Includes all abstracted logic in each time-frame • Solution: “Variable-time-frame” gate-level abstraction • Adds logic to each time-frames on demand (a gate may be added in one time-frame but not in others)
Improved BMC • In the classical BMC, in each timeframe, we add the complete “tent” (bounded cone-of-influence) • experiments show that a small fraction of this logic (typically, 5-20%) is enough to prove the problem UNSAT • This motivates a smarter approach • add logic on-demand • This may reduce the SAT solver size substantially, resulting in a faster and more scalable BMC Frame 3 Frame 2 Frame 1 Frame 0
Deciding What Logic to Add • It is enough to add only logic in the UNSAT cores • But we do not know what is the next UNSAT core • We use previous cores: • Lift K previous UNSAT cores to the given level • If the problem is still SAT, refine it by selectively adding gates to time-frames • Use the rollback feature of SAT solver to include the minimal amount of logic UNSAT core of Frame 3 UNSAT core of Frame 2 UNSAT core of Frame 1 UNSAT core of Frame 0
Improved Gate-Level Abstraction • Use the variable-time-frame approach to BMC • Then, build a gate-level abstraction, by taking the union of all gates, present in any time-frame
Improved Interpolation • Interpolation-based model checking can benefit from the variable-time-frame approach to BMC • When the transition relation is unrolled, there is no need to add all logic in the COI of the property • The proposed approach can be used to decide what logic to include • As a result • The SAT problem becomes simpler • The intermediate interpolants becomes smaller
Experimental Results abc 01> read ex1.aig; ps ex1: i/o = 1570/ 1 lat = 3113 and = 16745 lev = 31 abc 02> pdr Invariant F[29] : 5033 clauses with 734 flops (out of 3113) Property proved. Time = 808.01 sec abc 03> read ex1.aig; ps ex1: i/o = 1570/ 1 lat = 3113 and = 16745 lev = 31 abc 04> &vta -S 5 -P 2 -F 45 -v Solver UNSAT = 1.49 sec ( 14.50 %) Solver SAT = 2.57 sec ( 24.94 %) Refinement = 5.37 sec ( 52.17 %) Other = 0.86 sec ( 8.37 %) TOTAL = 10.29 sec (100.00 %) SAT vars = 36976. Clauses = 92646. Confs = 5074. Used 0.75 Mb for proof-logging. abc 05> &vta_gla; &ps; &gla_derive; &put; pdr Gate-level abstraction: PI = 1 PPI = 66 FF = 143 (4.59 %) AND = 505 (3.02 %) Invariant F[22] : 545 clauses with 114 flops (out of 143) Property proved. Time = 3.92 sec
25 : 147 617 9 3783 26 : 2 617 0 3806 27 : 118 628 22 4581 28 : 2 628 0 4602 29 : 144 629 1 5259 30 : 2 629 0 5290 31 : 125 635 7 5851 32 : 2 635 0 5929 33 : 160 640 1 6549 34 : 3 640 0 6570 35 : 212 650 11 7274 36 : 2 650 0 7295 37 : 217 650 0 7931 38 : 3 650 0 7952 39 : 229 650 5 8519 40 : 2 650 0 8540 41 : 295 650 0 9087 42 : 3 650 0 9109 43 : 296 650 0 9694 44 : 2 650 0 9715 SAT completed 45 frames. Time = 10.28 sec Solver UNSAT = 1.49 sec ( 14.50 %) Solver SAT = 2.57 sec ( 24.94 %) Refinement = 5.37 sec ( 52.17 %) Other = 0.86 sec ( 8.37 %) TOTAL = 10.29 sec (100.00 %) SAT vars = 36976. Clauses = 92646. Confs = 5074. Used 0.75 Mb for proof-logging. abc 02> &r ex1.aig; &ps abc 02> &vta -S 5 -P 2 -F 45 -v Frame Confl One Cex All 0 : 0 7 0 6 1 : 0 11 0 11 2 : 0 66 0 80 3 : 0 73 0 31 4 : 0 84 0 135 5 : 0 90 0 61 6 : 0 90 0 71 7 : 0 96 0 100 8 : 0 96 0 116 9 : 0 104 0 152 10 : 0 104 0 174 11 : 0 112 0 219 12 : 0 112 0 249 13 : 0 139 3 323 14 : 0 139 0 360 15 : 0 150 100 555 16 : 0 150 0 572 17 : 0 150 0 674 18 : 0 150 0 692 19 : 0 150 0 831 20 : 0 150 0 849 21 : 16 536 131 2112 22 : 0 536 2 2131 23 : 51 602 36 3057 24 : 2 602 0 3080
ABC’s &vta vs. IBM’s SixthSense • Tried two SixthSense configurations: • Config2: automatic, SAT-based, counter-example-based, gate-level, fixed time-frame • Config5: automatic, SAT-based, hybrid, gate-level, fixed time-frame • Used a suite of 58 model checking benchmarks submitted to HWMCC’11 by IBM • Result 1: Config5 produces abstractions that are 20% (16%) smaller in terms of gates (flops) • Result 2: Config2 completed more timeframes in 5 minutes for 75% of benchmarks
Conclusions Reviewed abstraction algorithms Motivated an improvement to BMC Connected it with gate-level abstraction Showed preliminary experimental results 15
Future Work • Using coarser objects to abstract, refine, and derive CNF • Adopting min-cut heuristics to decide what gates to add to the abstraction • Performing the initialized unrolling with proof-logging