A 3-V Fully Differential Distributed Limiting Driver for 40 Gb/s Optical Transmission Systems

1. A 3-V Fully Differential Distributed Limiting Driver for 40 Gb/s Optical Transmission Systems D.S. McPherson, F. Pera, M. Tazlauanu, S.P. Voinigescu Quake Technologies, Inc. Ottawa, ON, K2K 2T8, Canada

2. Outline • Overview • Device modeling • Circuit design and features • Measurement results • Summary

3. Design overview • Fully differential • AC coupled at the input • DC coupled to the modulator • Based on a 0.15 mm GaAs PHEMT technology • Uses double source follower inverter gain stages • Output drive stage is distributed • Operates in limiting mode • Includes additional control features

4. Scalable PHEMT model extraction • An accurate scalable model is essential for this design • It must capture the transistor’s characteristics over the entire bias range • For the present design, the Agilent EEsof Scalable Nonlinear HEMT model was used • The model is implemented in Agilent EEsof EDA’s Advanced Design System

5. Extraction geometries and conditions

6. Transfer characteristics

7. fT versus geometry and temperature

8. Differential output data  3 Vp-p per side Differential input data  0.5 …1.2 Vp-p per side Single-supply  –5.2 V DC power dissipation  2.8 W On-chip terminated  50 W Adjustable output offset  –0.15 … –1.1 V Adjustable duty cycle  30% … 70% Adjustable output amplitude  1.7 … 3.0 Vp-p per side Driver specifications

9. Circuit schematic

10. Gain block architecture

11. Distributed output stage

12. Pulse width control Output offset control Control function implementation

13. 1.95 mm 3.99 mm Chip microphotograph • Fabricated by Fujitsu Quantum Devices Limited • 0.15 mm AlGaAs/InGaAs PHEMT process • Substrate height of 28 mm • Single-metal layer with underpasses • Through-wafer vias for grounding • Schottky diodes • Epitaxial resistors

14. Anritsu MP1801A 43.5G Mux 86100A scope & 83484A 50 GHz mod. 20 dB attenuator 12” flexible 2.4 mm cables 60” flexible 2.4 mm cable for clock sync. 65 GHz GGB MCW with 150 mm pitch Setup for on-wafer eye measurements

15. BW = 16 GHz Bandwidth of measurement setup

16. 40 Gb/s eye-diagram (test setup) • Tr = 12.7 ps • Tf = 11.9 ps • Tj = 6.7 ps

17. 40 Gb/s 44 Gb/s Nominal eye-diagrams • Output swing of 3.0 Vp-p per side • Rise/fall times are 10.9/11.4 ps • Jitter is 8.6 ps (peak to peak)

18. Low amplitude Maximum offset Output swing of 1.7 V Offset of –1.2 V Control features applied at 40 Gb/s

19. 30% DCD 66% DCD Control features applied at 40 Gb/s

20. Summary • A full featured 3-V 40 Gb/s modulator driver has been designed and fabricated using a GaAs PHEMT process • Limitations associated with the technology, particularly its low fT, can be overcome in design • The design is very challenging because it involves a complex set of trade-offs • The result is a unique and robust circuit that exhibits excellent yield and performance

21. Acknowledgment • The authors would like to thank Fujitsu Quantum Devices Limited for fabricating the die • They would also like to express their gratitude to Quake colleagues H. Tran and D. Viorel for their valuable contributions