Computer Organization Lecture 21

1. Computer OrganizationLecture 21 Subroutines, stack Interrupts, service routines Input and output, buses University of Portland School of Engineering

2. Instruction flow • Most of the time: program executes sequentially unless a branch or jump requested • Sometimes • Programmer wishes to execute a subroutine, function, or method • An unusual event occurs internally or externally and the program needs to respond to it University of Portland School of Engineering

3. 1 2 Caller Callee 3 4 Subroutine flow control • Program prior to sub call • Caller transfers control to Callee • Callee transfers control to Caller • Program after sub call May be nested University of Portland School of Engineering

4. Hardware for subroutines • Goal • Jump to some memory location • Return back to next instruction after jump (PC-next) • Requirements • Save the value of the PC-next • Modify the PC, do the jump • Restore the value of PC to PC-next University of Portland School of Engineering

5. MIPS subroutines • Jump-and-link: jal • Saves PC-next in $ra • Jumps to subroutine address • Jump register: jr • Jumps to address in register • jr $ra will perform return • Use these to access subroutines University of Portland School of Engineering

6. Subroutine programming memory memory memory Call Call jal sub Call-next Call-next sub jr $ra return PC = Call $ra = xx PC = sub $ra = Call-next PC = Call-next $ra = Call-next University of Portland School of Engineering

7. How do we nest subroutines? University of Portland School of Engineering

8. Stack memory usage Push onto stack Pop from stack $sp points to top of stack University of Portland School of Engineering

9. Stack operations • Push sub $sp, $sp, 4 # push $ra on stack sw $ra, ($sp) • Pop lw $ra, ($sp) # pop $ra from stack add $sp, $sp, 4 Same operations to save registers University of Portland School of Engineering

10. Unusual events • Three types: all require immediate action • Internal to computer • Hardware generated • Software generated (OS requests) • External to computer: only hardware generated • Notation • MIPS: exception = internal, interrupt = external • Common: everything is an interrupt University of Portland School of Engineering

11. Identify possible events? University of Portland School of Engineering

12. Hardware for interrupts • Enable/disable: turns interrupts on and off • Controller changes and response • Finish instructions (flush pipeline) • Disable interrupts • Record type of event (Cause register) • Save return address (EPC register) • Branch (vector) to specific address (0x8000 0180) • Mechanism nearly identical to jal University of Portland School of Engineering

13. MIPS controller state diagram • Two sources: bad opcode, overflow • Cause register written • EPC written • PC written University of Portland School of Engineering

14. Interrupt request map University of Portland School of Engineering

15. Interrupt service routine • Save any registers used: save state on stack • Perform required action • Restore registers used: restore state from stack • Enable interrupts • May be done after registers saved • Provides for nested interrupts • Return University of Portland School of Engineering

16. Major computer components Five classic computer components University of Portland School of Engineering

17. Computer components • Input: receives information from external world • Output: transmits information to external world • Memory: holds programs and data • Data path: physical route that carries info • Control: coordinates overall flow of info University of Portland School of Engineering

18. System bus Bus interconnects system agents University of Portland School of Engineering

19. Adr, Data, Control MDP16 buses University of Portland School of Engineering

20. Early PC buses High speed Med speed CPU’s 8080 – 80486 vintage Slow speed University of Portland School of Engineering

21. Pentium 4 buses North bridge 82850 300/400 MHz RDRAM DIMMS South bridge 82801 6 Slots 100 Mbit University of Portland School of Engineering

22. ··· Agent 0 Agent n Signal 0 Signal 1 Bus ··· Signal n System view of a computer One Agent at-a-time owns the bus University of Portland School of Engineering

23. Example buses? University of Portland School of Engineering

24. Bus properties • Agents • Master: owns bus, issues requests • Slave: responds to requests from a master • Interconnections • Parallel, serial • Point-to-point, distributed • Single- and multi-master University of Portland School of Engineering

25. Bus properties, continued. • Electrical • Clocking: synchronous, asynchronous • Logic families: setup, hold, propagation • Physical: impedance, length, speed • Performance • Bandwidth or data rate, B/s • Turn-around time to change masters, t University of Portland School of Engineering

26. Find B/W of MDP16 memory? CLK = 200 ns, Width = 16-bits University of Portland School of Engineering

27. University of Portland School of Engineering

28. How do we nest subroutines? • Use stack pointer register ($sp) • Push $ra onto stack upon subroutine entry • Execute body of subroutine, may call other subroutines • Pop $ra from stack just before subroutine exit • Return from subroutine University of Portland School of Engineering

29. Identify possible events? • Overflow, underflow, divide-by-zero, parity or CRC error, illegal instruction • Memory or file protection (write to read-only, page fault) • Real time clock, OS request • Disk drive, CD, E-net: data transfer ready, or complete University of Portland School of Engineering

30. Example buses? • Uart • I/O • Address • PCI • ISA • S-ATA • USB http://en.wikipedia.org/wiki/Computer_bus University of Portland School of Engineering

31. Find B/W of MDP16 memory? CLK = 200 ns, Width = 16-bits University of Portland School of Engineering