Computer Organization Lecture 23

1. Computer OrganizationLecture 23 RAID Input/output design RS232 serial port example Direct memory access University of Portland School of Engineering

2. RAID • RAID: redundant arrays of inexpensive disks • History: Patterson, Gibson, Katz (1987); UC Berkeley • Goal: high speed, high reliability, low cost • Technique: place data across multiple drives and include redundancy (striping) • RAID levels: 0 – 6, define the striping University of Portland School of Engineering

3. Data striping • Bit level: each bit of a byte written on a different disk, along with parity • Block level: each byte of a file written to a different disk, along with ECC • LUN: collection of drives appear as one logical storage unit • Multiple, parallel drives: number often a factor of 8, increase bandwidth University of Portland School of Engineering

4. RAID example: 4 data disks University of Portland School of Engineering

5. Commercial product Features: 7TB, hot swappable (17 drives), 400 MB/s, 7200 rpm drives, $2/GB, RAID 0, 1, 3, 5, 0+1 University of Portland School of Engineering

6. ··· Agent 0 Agent n Signal 0 Signal 1 Bus ··· Signal n System view of a computer One Agent at-a-time owns the bus University of Portland School of Engineering

7. Bus timing Address Bus Driven Data Bus Driven Clk Breq Bgnt Ack ARB ADR DATA RESP University of Portland School of Engineering

8. I/O design • Memory-mapped • Shared memory and I/O addresses • Some addresses I/O devices, some memory • All memory instructions may operate on an I/O device • Separate I/O address space: called ports • Two address spaces: memory and I/O • Unique I/O instructions: in, out University of Portland School of Engineering

9. memory (low bits) Address A Qout Q Data D E decoder memory In 0 A 1 Q R/W R/W R/W (upper bits) D n E E From Lecture 14 General memory design University of Portland School of Engineering

10. Memory design guide • Bus lower addresses to all devices • Use upper addresses and decoder for device enables • Data bus and other control signals sent to all devices • No read-write signal for ROM • Bus outputs together because they are tri-stated University of Portland School of Engineering

11. 0 In 1 n E General I/O design I/O: D flip flops Address Qout Q Data D (Read, Write) Ctl Ctl E decoder Q D Ctl E University of Portland School of Engineering

12. I/O design guide • Use address, control, and decoder for device reads and writes • Data bus sent to all devices • Bus outputs together because they are tri-stated University of Portland School of Engineering

13. Example I/O design • Bus (simplified) • Address: 8-bit • Data: 8-bit, tri-state (uni-directional) • Control: read, write • I/O addresses (Port addresses) • Device 0 = 0xf8 • Device 1 = 0xf9 University of Portland School of Engineering

14. Schematic University of Portland School of Engineering

15. Trace Write to Ports Read from Ports Bus floats to 0xff Bus floats to 0xff University of Portland School of Engineering

16. Find decode logic for 4 ports? Port addresses = 0xf8, 0xf9, 0xfa, 0xfb University of Portland School of Engineering

17. Trace Write to Ports Read from Ports Bus floats to 0xff Bus floats to 0xff University of Portland School of Engineering

18. RS-232 serial port • I/O device: USART (universal synchronous asynchronous receiver transmitter) • Functionality (similar to shift register) • Transmitter: parallel in, serial out • Receiver: serial in, parallel out • Status • Output buffer empty • Input buffer full University of Portland School of Engineering

19. C8251 block diagram serial out parallel in parallel out serial in University of Portland School of Engineering

20. USART addressing • Memory-mapped I/O (MIPS approach) • Receiver • Control register: 0xffff 0000 • Data register: 0xffff 0004 • Transmitter • Control register: 0xffff 0008 • Data register: 0xffff 000c University of Portland School of Engineering

21. USART assembly code Definitions for memory-mapped devices University of Portland School of Engineering

22. Receive, transmit subroutines Subroutines to read and write a byte University of Portland School of Engineering

23. Find flowchart for rcvbyte? University of Portland School of Engineering

24. Wait (busy) loop • Programming technique • CPU continuously reads control register until non-zero (ready bit set): wait loop • CPU reads/writes data to port • Results in poor system utilization: both memory-mapped or separate I/O addresses • Known as programmed I/O University of Portland School of Engineering

25. Disadvantages of programmed I/O? University of Portland School of Engineering

26. Direct memory access • Objective: avoid the disadvantages of programmed I/O (eliminate busy loop) • Technique • CPU writes to special controller (word count and memory address) • CPU tells controller to start data transfers • CPU continues with other computing • CPU responds to interrupt from controller: ISR University of Portland School of Engineering

27. Role of DMA controller • Accept initialization data from CPU • Access I/O device and drive bus (master) • Input: read I/O device and write data to memory • Output: read memory data and write to I/O device • Interrupt CPU when transfer complete University of Portland School of Engineering

28. Read I/O Write memory Programmed I/O Programmed I/O ties up CPU University of Portland School of Engineering

29. Initialize Multiple transfers DMA I/O DMA requires little CPU overhead University of Portland School of Engineering

30. ISR ISR Interrupt Interrupt DMA time line CPU and I/O concurrent in time University of Portland School of Engineering

31. University of Portland School of Engineering

32. Find decode logic for 4 ports? University of Portland School of Engineering

33. Push $ra Get rcv status Char ready? Read and echo char Pop $ra Find flowchart for rcvbyte? no yes University of Portland School of Engineering

34. Disadvantages of programmed I/O? • CPU cycles result in little computing • Memory continuously accessed, possible contention with another CPU • One I/O access at a time • Bus heavily requested University of Portland School of Engineering