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Architectures & Digital IC design

Architectures & Digital IC design. ORGANIZATION. Advanced Design Departements ( Architecture Design Laboratory of CEA ) Jean-René LEQUEPEYS lequepeys@chartreuse.cea.fr - 33 (0)4 38 78 37 49 Grenoble Thierry COLLETTE Thierry.collette@cea.fr - 33 (0)1 69 08 65 25 Paris.

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Architectures & Digital IC design

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  1. Architectures&Digital IC design

  2. ORGANIZATION Advanced Design Departements(Architecture Design Laboratory of CEA)Jean-René LEQUEPEYS lequepeys@chartreuse.cea.fr - 33 (0)4 38 78 37 49 Grenoble Thierry COLLETTE Thierry.collette@cea.fr - 33 (0)1 69 08 65 25 Paris

  3. ASIC Design Activities • Integrated circuit design (ASIC) : analog, mixed and RF • Parameter extraction of technologies – Component modeling • Architecture design : parallel and reconfigurable • Design of Integrated Circuits forCEA projects (40 %) • ASIC & IP design for partners (60%) • Design of ASIC and ASIP on emerging technologies (advanced CMOS, MEMs…) • Validation of new concepts (heterogeneous design, advanced architectures).Patents on architecture, schemes, topologies • Applications fields : smart card, telecom, automotive, imagers, biochips, multimedia…

  4. Design Activities • Staff . 90 Full Time CEA Designers . + 29 PhD & Postdocs . + Students • About 15-20 Design per year • R&D of advanced design methodology • More than 700 Masks design per year (sensors, actuators, detectors, etc.)

  5. Growth of Design Activities CEA, PhDs, Post-docs 100 80 60 50 40 20 0 1 2 3 4 2001 2002 2003 2004 CEA PhDs, Post-docs

  6. Design Activities organization Imaging systems & Biochips Digital Architectures Test and Reliability Energy and Power mngt Layout/Mask Ad. Techno Processor and multi-processor Architectures Reconfigurable computing RF architecture & circuit

  7. Design Activities : Main Partners Academic / Institutes • CSEM • INPG/TIMA • IMEC • IMST • EPFL • IMEP • ESE • ESIEE • INRIA • … Industrials partners • THALES, EADS • STMicroelectronics, INFINEON, PHILIPS, ATMEL • BICRON ST GOBAIN • NOKIA, MOTOROLA, PHILIPS • SOFRADIR, TRIXEL, ULIS • ALCATEL, SIEMENS • SIEMENS TRANSPORTATION SYSTEM • GEMPLUS

  8. Design : Technology addressed today • ASIC Design . Standard Cells (Digital & Mixed ICs) . Full Custom (Analog & Mixed ICs) • Addressed technologies • ATMEL CMOS 0.35 µm, CMOS 0.5 µm • STMICROELECTRONICS CMOS 0.09 µm, CMOS 0.13 µm, CMOS 0.18 µm, CMOS 0.25 µm, BICMOS6 0.35 µm, BICMOS7 0.25µm CMOS/SOI 0,13 µm • AMS CMOS 0.35 µm, 0,8µm • AMI BCD CMOS 0.7 µm • MOTOROLA BCD 0.25 µm

  9. Design Activities - EDA Tools & Equipments • CAD for ICs design CADENCE (Analog/Digital/RF) MENTOR GRAPHICS (Analog/Digital/RF) SYNOPSYS (Digital IC's) AGILENT (RF IC's) • Modeling software's : MATLAB/SIMULINK, SystemC, ARM9xx and PowerPC… • Test and characterization on wafers and encapsulated circuits • Equipment for parameters extraction

  10. Test and characterization • On wafer test and characterization • Embedded reliability • RF test and characterization • Noise characterization • Parametersextraction

  11. Research domains Prototyping IC Application demonstrators Telecom and multimedia applications Design methodology Mastering the chip complexity and preparing solutions for advanced CMOS technologies Digital Architectures Parallel architectures Network On Chip GALS Architectures Low-power Reconfigurable architectures

  12. Technical challenges FRESH : “Flexible and Reconfigurable Embedded Software and Hardware” • Prototyping Integrated Circuits • Telecom and Multimedia Applications: e.g., MC-CDMA Chip • Reconfigurability in terms of computing, control and communication resources • Network on Chip based architecture • Asynchronous mechanisms for communication purposes • Associated design flow and mapping tools

  13. Integrated Circuit HW Reconfigurable Computing IPs IPs IPs FPGA CO-DESIGN TOOLS & DEVELOPMENT ENVIRONMENT Interconnexion Network ………. µProc MEM I/O µProc DSP Interface µProc MEM I/O µProc MEM I/O Other system SW FRESH Generic Platform Architecture • Prototyping integrated circuit, e.g. for MC-CDMA • Flexible & Reconfigurable ICs • Integration of a large number of computing resources • Well-defined interfaces between communication and computing resources • Communication systems based on a distributed network • Network extension outside IC to increase functionalities & performances • Associated co-design tools

  14. Host Control (task scheduling, parallelism control and reliability) Sparc Sparc Sparc Computing (parallelism and reconfigurable computing) Processingboards Processingboards Processingboards boards boards boards Racks PE Registers PU PU PU PE PE ALU Reconf Processors Processing Unit PU PU PU PE PE UC + Mem PE PE PU PU PU PE Supercomputer architecture User

  15. Control Computing Multicore architecture component • TLP et RPU • Reconfigurable Interconnections • Complexity managment • Embedded reliability • Energy managment • Advanced technologies • Reconfigurable coprocessors OS Scheduling, … Switch and interconnection RISC core RISC core L2 L2 L1 L1 RISC core RISC core L1 L1 RISC core RISC core L1 L1 RPU fg core RPU cg core L1 L1

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