Accuracy-Configurable Adder for Approximate Arithmetic Designs

1. Accuracy-Configurable Adder for Approximate Arithmetic Designs Andrew B. Kahng, Seokhyeong Kang VLSI CAD LABORATORY, UC San Diego 49th Design Automation Conference June 6th, 2012

2. Outline • Background and Motivation • Accuracy Configurable Adder Design • Experimental Setup and Results • Conclusions and Ongoing Works

3. Why Approximate Designs? • Threats to traditional IC design approach ... Extreme variations: PVT variation uncertainty lead to design overhead Reliability issues: Hard errors (NBTI, latchup), Soft errors (α-particle) Cost: Cost (power/performance) of perfect accuracy is too high! • Approximate designs Relaxing the requirement of correctness can dramatically reduce costs of the design • Threats to traditional IC design approach ... Extreme variations / Reliability issues / Cost: • Approximate designs Relaxing the requirement of correctness can dramatically reduce costs of the design What is the square root of 10 ? “a little more than three” Approximation could be faster and more powerful “3.162278....”

4. Previous Approximate Adders Lu et al. IEEE Computer 2004 • Faster adder w/ shorter carry chain • High performance with small error rate • Large area overhead: not applicable for low energy design Zhu et al. TVLSI 2010 • ETAI : accurate part + inaccurate part • Reduce error size • Error rate is high • Output accuracy is fixed  benefitscan be limited by required accuracy

5. Our Work: Accuracy-Configurable Approximate Adder How power benefits can be achieved … • Accuracy-configurable design adapts to changing requirements by using different modes in each situation

6. Our Work: Accuracy-Configurable Approximate Adder How power benefits can be achieved … • Accuracy-configurable approximate adder error collection(ECC-2) error collection(ECC-1) approximate adder accuracy: 90% accuracy: 95% accuracy: 100% Mode 1: turn-off ECC-1, ECC-2 Mode 2: turn-off ECC-2 Mode 3: turn-on All ECC

7. Outline • Background Motivation • Accuracy Configurable Adder Design • Experimental Setup and Results • Conclusions and Ongoing Works

8. Approximate Adder Implementation 16-bit adder case • Carry chain is cut to reduce critical path delay • Sub-adders generate results of partial summation • Middle sub-adder improves accuracy (error 50%  5.5%)

9. Approximate Adder Implementation N-bit adder case carry Probability of correct result : Estimation over CLA (N=16) • Approximate adder can be configured with “k”

10. Error Detection and Correction Variable latencyoperation • Error can be detected and corrected with small overhead • Error detection: ‘and’ gates • Error correction: incrementor circuit • Error detection and correction can take more time than critical path delay of “sub-adder”; the throughput can be reduced

11. Accuracy Configuration with Pipeline power gating power gating power gating • Each stage generates a result with different accuracy • Can turn off later stages with power gating according to accuracy requirement

12. Outline • Background Motivation • Accuracy Configurable Adder Design • Experimental Setup and Results • Conclusions and Ongoing Works

13. Experimental Setup and Metrics • Experimental Setup • Library: TSMC 65GP • Implementation: Synopsys Design Compiler • Simulation: Cadence NC-SIM • Input patterns: random data and actual data • Library preparation: Cadence Library Characterizer • Accuracy Metrics • Rc and Re : correct and obtained results • Be: number of error bits, Bw: bit-width of data

14. Approximate Adder Comparison • Accuracy vs. power consumption Image smoothing (Gaussian filter) Original image Accurate adder ACA (PSNR 24.5dB) ETAI (25.3dB) ETAII (16.2dB) LU (11.1dB) (a) (b) (c) (c)~(f) have 50% power of accurate adder (b) (d) (e) (f) * ETAI cannot detect and correct errors

15. Approximate Adder Comparison • Accuracy vs. power consumption w/voltage scaling Voltage scaling (1.0V~0.6V) • ACA adder shows fine results (accuracy vs. power) on both ACCamp and ACCinf metrics

16. Accuracy Configuration and Power Saving • Power saving from voltage scaling + mode change 4-stage 32-bit adder case accurateresult Accuracy: 1.0 → 0.9 voltage scaling mode change 4X reduction voltage scaling mode change • Accuracy configuration w/ mode change is more effective than w/ voltage scaling

17. Accuracy Configuration and Power Saving • Power consumption when accuracy requirement is varying (w/ SPEC 2006 benchmarks) High accuracy Average 30% power savings over no accuracy configuration

18. Outline • Background Motivation • Accuracy Configurable Adder Design • Experimental Setup and Results • Conclusions and Ongoing Works

19. Conclusions and Ongoing Works • Conclusions • We proposed accuracy-configurable approximate (ACA) adder, which can adapt to changing accuracy requirement • ACA can provide 30% power reduction with accuracy configuration during runtime • Ongoing Works • Accuracy-configurable design for other arithmetic units (multiplier, divider) • Automated synthesis flow (minimize power under the required accuracy) RTL Required accuracy exact adder Accuracy estimation approximate adder Synthesis

20. Thank You!

21. Accuracy-Configurable Approximate Design • Required accuracy can change during runtime • Idea of High-Efficiency Math highlighted by Intel Labs at ISSCC-2012 • Variable-precision floating point unit w/ accuracy tracking : 24-bit  12-bit 6-bit as needed • Accuracy-configurable design adapts to changing requirements, maximizing benefits of approximate design paradigm Variable-precision Mantissa