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High-speed Addition with Bipolar Digital Circuits

High-speed Addition with Bipolar Digital Circuits. Matthew W. Ernest Rensselaer Polytechnic Institute. Carry types: Carry Select. Compute possible results in parallel Select when actual carry-in available Requires internal carry for blocks, e.g. ripple Delay: O(f(n/b) +b)

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High-speed Addition with Bipolar Digital Circuits

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  1. High-speed Addition with Bipolar Digital Circuits Matthew W. Ernest Rensselaer Polytechnic Institute

  2. Carry types: Carry Select • Compute possible results in parallel • Select when actual carry-in available • Requires internal carry for blocks, e.g. ripple • Delay: O(f(n/b) +b) • Area: O(f(n/b)·b+b) • Affected by block sizing 1 1 0 0

  3. Carry Select Delay Path • t=0..4: Each block operates in parallel • t=5: Carry-out of first block selected by carry-in, no activity in second block • t=6: Carry-out of second block selected by carry-out of first 1 b7…b4 0 1 b7…b4 0 6 5 4 3 2 1 0 t

  4. Lengthening non-critical paths • t=0..4: Each block operates in parallel • t=5: Carry-out of first block selected by carry-in, additional bit handled during delay • t=6: Carry-out of lengthened second block selected by carry-out of first 1 b8…b4 0 1 b7…b4 0 6 5 4 3 2 1 0 t

  5. Carry Select Delay • td: delay of circuit • tg: delay of gate • tm: delay of mux • N: # of stages • ci: bits in stage i Given: td = tg· ci + N · tm If: tg· ci+1£ tg· ci + tm Define: s = ci+1 - ci£ tm / tg

  6. Minimizing delay via stage size td / tg = éÖ2 B s + s/2ù N =étd / tg - s/2 ± Ö(td / tg - s/2)2 - 2 B sù s c1 =td / tg- Ns

  7. Carry Types: Block carry look-ahead • A block propagates a carry if all bits in the block propagate a carry • A block generates a carry if a bit generates a carry and all succeeding bits propagate • Delay: O(log n) • Area: O(n log n)

  8. Carry vs. Pseudocarry Cout=Gn+ Pn• Gn-1 +…+Pn• Pn-1• ... P0• Cin If G=A•B and P=A+B then G=G•P Cout= Pn•Gn+ Pn• Gn-1 +…+Pn• Pn-1• ... P0• Cin Cout= Pn(Gn+ Gn-1 +…+Pn-1• ... P0• Cin) Cout= Pn•Hn Hn =Gn+ Gn-1 +…+Pn-1• ... P0• Cin

  9. Deriving Block Pseudocarry from Carry Lookahead Terms Block Generate: Gi•j0= Gij + PijGij-1i + … + PijPij-1iPij-2i•••Gi0 If G=A•B and P=A+B then G=G•P Gi•j0= PijGij + PijGij-1i + … + PijPij-1iPij-2i•••Gi0 Gi•j0= Pij(Gij + Gij-1i + … + Pij-1iPij-2i•••Gi0) Hi•j0= Gij + Gij-1i + … + Pij-1iPij-2i•••Gi0

  10. Generalized Pseudocarry Equations H2s= G1s+1 + G1s Hi+js= Hjs+i + Ijs+i-1•His Hi+j+ks= Hks+I+j + Iks+I+j-1•Hjs+i + Iks+I+j-1• Ijs+i-1•His Ip+qt= Iqt+p•Ipt Ip+q+rt= Irt+q+p•Iqt+p•Ipt

  11. Generating Sums Using Pseudocarry Sn=AnÅBnÅCn-1 If Tn=AnÅBn Cm= Pm•Hm then Sn=TnÅPn-1Hn-1

  12. Pseudocarry Blocks H2s H2s H2s H2s H2s H2s H2s H2s H2s H2s H2s H2s H2s H2s H2s H2s H6s H6s H6s H6s H6s H18s H14s H32s

  13. CML/ECL Current Steering Gates

  14. Any function of inputs • Fan-in limited by supply voltage • Limited to simple functions • Large fan-in Single-ended vs. Double-ended

  15. Look-ahead gate w/ fully differential logic Hn-2 Hn-2 Hn-1 Hn-1 In-1 In-1 In In Hn-1 Hn-1 Hn Hn In In Hn Hn

  16. Hn Hn-1 Vr Hn Vr In In Mixed input look-ahead gates • In(Hn+ Hn-1) + In•Hn • Hn+ In•Hn-1 • Two series-gated levels for three inputs

  17. Hn Hn-1 Hn Hn-2 Hn-1 Hn In-1 In-1 In In Mixed input look-ahead gates • In In-1(Hn+ Hn-1 + Hn-2) + In In-1(Hn+ Hn-1) + In• In-1• Hn • Hn+ In•Hn-1 + In• In-1• Hn-2 • Three series-gated levels for five inputs

  18. Adder comparision CSel PCLA Ripple CLA Bits C B A 32 32 12 12 9 6 5 64 64 20 16 12 7 6

  19. Pseudocarry Tree Oscillator Select 0 1 31 32 1 B A Cin Cout

  20. 2 x 165 ps Carry Tree High-speed Output

  21. Comparisons of Published Adders

  22. Minimize/Balance Wiring Length Cartesian Alignment

  23. Minimize/Balance Wire Length Isometric Alignment

  24. Cascode Output Stage • Eliminates capacitive coupling between input and output • Shortens rise time, but increases delay

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