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Bistable Bit Representation (dual-rail encoding). AND Gate. Outputting 0. Outputting 1. OR Gate. Outputting1. Outputting 0. XOR Gate. Outputting 1. Outputting 0. Logic Gates. D Latch. Adding control reactions. Synchronous Sequential Computation. Sustained Oscillations.
E N D
AND Gate Outputting 0 Outputting 1
OR Gate Outputting1 Outputting 0
XOR Gate Outputting 1 Outputting 0
D Latch Adding control reactions
Sustained Oscillations Transfer concentrations in alternating phases:red, green and blue.
First Attempt… R, G, and B converge!
Implementing D Flip Flop Master-slave configuration
Implementing Memory D1’ D1 D2’ D2 Blue phase: Red phase: