Synthesis of multiple rail phase encoding circuits

1. Synthesis of multiple railphase encoding circuits Andrey Mokhov, Crescenzo D’Alessandro, Alex Yakovlev Microelectronics System Design Group, School of EECE, Newcastle University, UK {andrey.mokhov, crescenzo.dalessandro, alex.yakovlev}@ncl.ac.uk ASYNC Symposium, May 2009

2. Outline • Phase encoding • Conditional partial order graphs • Circuit synthesis • Phase detector • Matrix phase encoder • One hot phase encoder • Binary phase encoder • Conclusions and future work Outline ASYNC Symposium, May 2009

3. Phase encoding • Self-synchronous data communication protocol introduced by D'Alessandro et al [ PATMOS’05 ] • Reliability to single event upsets • High information capacity • No scalable implementations of multiple rail controllers ‘abdc’ symbol sensitive interval 4-wire channel: 4! = 24 symbols > 24 = 16 binary symbols log(n!) ≈ n·log(n) Phase encoding ASYNC Symposium, May 2009

4. Specification and synthesis of phase encoders • n-wire phase encoder exhibits n! different behavioural scenarios • STG/FSM specification size explosion: every scenario is specified explicitly • State space is exponential w.r.t. the channel width n. Structural synthesis method is required • Phase encoders convert data between two different domains: • Combinatorial codes, e.g. binary or one-hot encoded data • Sequences of events ordered in time Phase encoding ASYNC Symposium, May 2009

5. n-wire phase encoding channel Phase encoding ASYNC Symposium, May 2009

6. Outline • Phase encoding • Conditional partial order graphs • Circuit synthesis • Phase detector • Matrix phase encoder • One hot phase encoder • Binary phase encoder • Conclusions and future work Outline ASYNC Symposium, May 2009

7. Partial orders • Basic mathematical structure to describe event orders • Concurrency can be modelled • Choice cannot be modelled Conditional Partial Order Graphs ASYNC Symposium, May 2009

8. Conditional Partial Order Graphs [ DATE’08 ] Conditional Partial Order Graphs ASYNC Symposium, May 2009

9. CPOG-based synthesis flow Conditional Partial Order Graphs ASYNC Symposium, May 2009

10. Application examples Conditional Partial Order Graphs ASYNC Symposium, May 2009

11. Synthesis of phase encoders • CPOG model can be used for phase encoding controllers specification and synthesis: • Vertices correspond to the signal transitions in the channel • Conditional arcs determine the order of the transitions • 2-wire phase encoder specification example: Conditional Partial Order Graphs ASYNC Symposium, May 2009

12. Outline • Phase encoding • Conditional partial order graphs • Circuit synthesis • Phase detector • Matrix phase encoder • One hot phase encoder • Binary phase encoder • Conclusions and future work Outline ASYNC Symposium, May 2009

13. n-wire phase encoding channel Circuits synthesis ASYNC Symposium, May 2009

14. Phase detector • Decodes phase encoded symbols by detecting the relative order between all the pairs of transitions • Consists of n(n-1)/2 mutual exclusion (mutex) elements Circuits synthesis ASYNC Symposium, May 2009

15. Outline • Phase encoding • Conditional partial order graphs • Circuit synthesis • Phase detector • Matrix phase encoder • One hot phase encoder • Binary phase encoder • Conclusions and future work Outline ASYNC Symposium, May 2009

16. Matrix phase encoder • Generates phase encoded symbols given the matrix X = {xkj} of pairwise comparisons of the output transitions 1 → 2 → 3 1 → 3 → 2 2 → 1 → 3 2 → 3 → 1 3 → 1 → 2 3 → 2 → 1 Circuits synthesis ASYNC Symposium, May 2009

17. Matrix phase encoder (implementation) Circuits synthesis ASYNC Symposium, May 2009

18. Matrix phase encoder (implementation) Circuits synthesis ASYNC Symposium, May 2009

19. Outline • Phase encoding • Conditional partial order graphs • Circuit synthesis • Phase detector • Matrix phase encoder • One hot phase encoder • Binary phase encoder • Conclusions and future work Outline ASYNC Symposium, May 2009

20. One hot phase encoder • Generates phase encoded symbols given one hot data X = {x1…xn!} Circuits synthesis ASYNC Symposium, May 2009

21. One hot phase encoder (logic optimisation) • The synthesised CPOG can be optimised Circuits synthesis ASYNC Symposium, May 2009

22. One hot phase encoder (controller) Circuits synthesis ASYNC Symposium, May 2009

23. Speed-independent one hot phase encoder Circuits synthesis ASYNC Symposium, May 2009

24. Outline • Phase encoding • Conditional partial order graphs • Circuit synthesis • Phase detector • Matrix phase encoder • One hot phase encoder • Binary phase encoder • Conclusions and future work Outline ASYNC Symposium, May 2009

25. Binary phase encoder • Data is normally given in binary form • Binary phase encoder generates phase encoded symbols given binary encoded data Circuits synthesis ASYNC Symposium, May 2009

26. Outline • Phase encoding • Conditional partial order graphs • Circuit synthesis • Phase detector • Matrix phase encoder • One hot phase encoder • Binary phase encoder • Conclusions and future work Outline ASYNC Symposium, May 2009

27. Conclusions and future work • The work presents a scalable approach for synthesis of multiple rail phase encoding circuits • The approach uses the CPOG model in order to avoid exponential explosion of STG specifications due to duplication of events • Phase encoders are synthesised for matrix, one hot, and binary source encodings, but the approach can be easily adapted for the other encodings, e.g. m-of-n encoding • The future work includes the development of automated synthesis tools based on the presented theoretical techniques Conclusions and future work ASYNC Symposium, May 2009

28. End Thank you! Questions? ASYNC Symposium, May 2009

29. STG specification explosion ASYNC Symposium, May 2009

30. STG specification explosion ASYNC Symposium, May 2009

31. First scenario STG specification explosion ASYNC Symposium, May 2009

32. First scenario Second scenario STG specification explosion Event duplication! ASYNC Symposium, May 2009

33. STG specification explosion + Reduces event duplication + Can be synthesised automatically (e.g. Petrify) – Difficult for manual design – Not visual – Contains a lot of additional places to track the choices – Very time consuming to generate ASYNC Symposium, May 2009

34. End Thank you! More Questions? ASYNC Symposium, May 2009