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PCI-Express Network Sniffer Characterization Presentation Project Period : 2 semesters

PCI-Express Network Sniffer Characterization Presentation Project Period : 2 semesters. Students: Neria Wodage Aviel Tubul Advisor: Mony Orbach. 17/12/2007. Motivation & Introduction.

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PCI-Express Network Sniffer Characterization Presentation Project Period : 2 semesters

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  1. PCI-Express Network SnifferCharacterization PresentationProject Period: 2 semesters Students: Neria Wodage Aviel Tubul Advisor: Mony Orbach 17/12/2007

  2. Motivation & Introduction The increasing demand for Internet requires a real-time monitoring & filtering system for the large amounts of data passing through the net. PCI-Express is the most common high-speed serial bus in PC computers with a performance of up to 2.5Gbps.

  3. Project goals • Developing a controlled hardware sniffer enables monitoring and filtering data on real-time and transport filtered data to the PC through the PCIe bus. • Implementation of the system on Altera PCIe board with Stratix II GX FPGA.

  4. Ethernet PC System Environment Description Stratix II GX PCIe board

  5. Top Level Block Diagram Extrnal Ethernet 10/100 Mbps To PC Sniffer Ethernet MAC PCIe Interface 2.5 Gbps Develop the sniffer with the ability to filter data according to required parameters: IP Address \ MAC Address\ TCP \ UDP. (winter - spring) Connect system to the PC with a PCIe interface in order to control and introduce data. Based on AlteraPCIe IP Core. (spring) Implementation of the Ethernet interface Altera IP Core, using the Nios II processor to handle the TCP\IP protocol. (winter)

  6. Sniffer Abstract Diagram Sniffer Tx DATA 8-32 bit Filter Rx DATA 8-32 bit Filtered Rx DATA start\end _Packet Control PCIe Side Filter Required Parameters Ethernet Side

  7. HW & SW Tools SW: • Quartus II – • Nios II – • SoPC Builder - • Megacore-IP library - • HDL-Designer – HW: • PCIe Development Board -

  8. Tasks and schedule – part A 1. Studying basic net structure and Ethernet-TCP\IP protocols – done. 2. Learning the Altera Ethernet IP Core – in progress. 3. Learning NIOS II software environment – 20/12/07 4. Develop the Ethernet MAC block – 31/12/08 5. Execute logic simulation of the Eth. MAC – 3/1/08

  9. Tasks and schedule – part A 6. Mid presentation 10-13/1/08(according advisor coordination). 7. Sniffer logic design – 6/2/08 8. Performing simulation & elementary checks – 13/2/08 9. Final presentation of part A – 18-20/2/08

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