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Bruce Mayer, PE Registered Electrical & Mechanical Engineer BMayer@ChabotCollege.edu

Engineering 43. Diodes-1. Bruce Mayer, PE Registered Electrical & Mechanical Engineer BMayer@ChabotCollege.edu. Learning Goals. Understand the Basic Physics of Semiconducotr PN Junctions which form most Diode Devices Sketch the IV Characteristics of Typical PN Junction Diodes

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Bruce Mayer, PE Registered Electrical & Mechanical Engineer BMayer@ChabotCollege.edu

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  1. Engineering 43 Diodes-1 Bruce Mayer, PE Registered Electrical & Mechanical EngineerBMayer@ChabotCollege.edu

  2. Learning Goals • Understand the Basic Physics of Semiconducotr PN Junctions which form most Diode Devices • Sketch the IV Characteristics of Typical PN Junction Diodes • Use the Graphical LOAD-LINE method to determine the “Operating Point” of Nonlinear (includes Diodes) Circuits

  3. Learning Goals • Analyze diode-containing Voltage-Regulation Circuits • Use various math models for Diode operation to solve for Diode-containing Circuit Voltages and/or Currents • Learn The difference between LARGE-signal and SMALL-Signal Circuit Models IDEAL and PieceWise-Linear Models

  4. Diodes are ONE-Way Devices • Diodes exhibit a form of RECTIFICATION • i.e., It allows current to Flow in the FORWARD direction, But NOT in the REVERSE direction • Think of a diode as a“Check-Valve” for Electrical Current” • The Voltage Polarity Across a Diode is Called its “Bias” Voltage • FORWARD Bias → Flow ALLOWED • REVERSE Bias → NO Flow Allowed

  5. Basic Concepts • Diodes are extremely Important Devices as they perform the RECTIFICATION operation • Rectification means that current can (usually) Flow in ONE direction, and NOT the Other • The Circuit Symbol • Notation: vD & iD represent the INSTANTANEOUS diode voltage & current • Notice • Anode → + terminal • Cathiode → − terminal

  6. Diodes are highly NONlinear • Note • Fairly SHARP CORNERS • FLAT Region • Changes in CONCAVITY • Three Distinct OPERATING REGIONS Typical Rectifying-Diode V-I Curve Rectification

  7. Diode Physics  Materials • Silicon (Si) and Germanium (Ge) are the two most common single elements that are used to make Diodes. A compound that is commonly used is Gallium Arsenide (GaAs), especially in the case of LEDs because of it’s large bandgap. • Silicon and Germanium are both group 4 elements, meaning they have 4 valence electrons. Their structure allows them to grow in a shape called the diamond lattice. • Gallium is a group 3 element while Arsenide is a group 5 element. When put together as a compound, GaAs creates a zincblend lattice structure. • In both the diamond lattice and zincblend lattice, each atom shares its valence electrons with its four closest neighbors. This sharing of electrons is what ultimately allows diodes to be build. When dopants from groups 3 or 5 (in most cases) are added to Si, Ge or GaAs it changes the properties of the material so we are able to make the P- and N-type materials that become the diode. The diagram above shows the 2D structure of the Si crystal. The light green lines represent the electronic bonds made when the valence electrons are shared. Each Si atom shares one electron with each of its four closest neighbors so that its valence band will have a full 8 electrons.

  8. N-Type (Negative) Material When extra valence electrons are introduced into a material such as silicon an n-type material is produced. The extra valence electrons are introduced by putting impurities or dopants into the silicon. The dopants used to create an n-type material are Group V elements. The most commonly used dopants from Group V are arsenic, antimony and phosphorus. The 2D diagram to the left shows the extra electron that will be present when a Group V dopant is introduced to a material such as silicon. This extra electron is very mobile.

  9. P-Type (Positive) Material p-type material is produced when the dopant that is introduced is from Group III. Group III elements have only 3 valence electrons and therefore there is an electron missing. This creates a hole (h+), or a positive charge that can move around in the material. Commonly used Group III dopants are aluminum, boron, and gallium. The 2D diagram to the left shows the hole that will be present when a Group III dopant is introduced to a material such as silicon. This hole is quite mobile in the same way the extra electron is mobile in a n-type material.

  10. P & N Type Semi Matls Brought Together to form a METALLURICAL (seamless) Junction The HUGE MisMatch in Carrier Concentrations Results in e- & h+ Cross DIFFUSION P-N Junction (Diode) Physics • Carrier Diffusion • e- Diffuse in to the P-Type Material • h+ Diffuse in to the N-Type Material

  11. In a p-n JCN Carrier Cross-Diffusion is SELF-LIMITING The e-/h+ Diffusion leaves Behind IONIZED Atom Cores of the OPPOSITE Charge The Ion Cores set up an ELECTRIC FIELD that COUNTERS the Diffusion Gradient P-N Junction Physics cont. E-Field • For Si the Field-Filled Depletion Region • E-Field  1 MV/m • Depl Reg Width, xd = 1-10 µm • E-fld•dx  0.6-0.7 V • “built-in” Potential

  12. A Rectifier is a “Check Valve” for Current flow Current Allowed in ONE Direction but NOT the other Side Issue → “Bias” Voltage A “Bias” Voltage is just Another name for EXTERNALLY APPLIED Voltage P-N Junction Rectifier E-Field

  13. p-n junction Rectification A small “Forward Bias” Voltage results in Large currents Any level of “Reverse” Bias results in almost NO current flow Class Q: For Fwd Bias, Which End is +; P or N??? P-N Junction Rectifier cont E-Field • A: the P end • The Applied Voltage REDUCES the internal E-Field; This “Biases” The Junction in Favor of DIFFUSION

  14. p-n junction No Applied Voltage P-N Junction Rectifier cont.2 • Internal Field ENHANCED • Carriers Pulled AWAY from Jcn; xd grows • Forward Bias Xd • Diffusion & E-Field in Balance, No Current Flows • Reverse Biased • Internal Field REDUCED • Carriers PUSHED and Diffuse to the Jcn where they are “injected” into the other side; xd Contracts

  15. Properties of Rectifying Junctions Reverse Forward • IN914 PN Diode • IF = 75 000 µA • IR = 0.025-50 µA

  16. The BIASED P-N Junction • “Bias” Simply refers whether the PN Junction will allow current to flow or not • Forward Bias: Vapplied > 0 (Anode Positive) • In forward bias the depletion region shrinks slightly in width. With this shrinking the energy required for charge carriers to cross the depletion region decreases exponentially. Therefore, as the applied voltage increases, current starts to flow across the junction. The barrier potential of the diode is the voltage at which appreciable current starts to flow through the diode. The barrier potential varies for different materials. • The Barrier Potential for Silicon is 0.6-0.7 volts

  17. The BIASED P-N Junction • “Bias” Simply refers whether the PN Junction will allow current to flow or not • Reverse Bias: Vapplied < 0 (Anode Negative) • Under reverse bias the depletion region widens. This causes the electric field produced by the ions to cancel out the applied reverse bias voltage. A small leakage current, Is (saturation current) flows under reverse bias conditions. This saturation current is made up of electron-hole pairs being produced in the depletion region. Saturation current is sometimes referred to as scale current because of it’s relationship to junction temperature

  18. iD (mA) Knee IS VBR vD ~V (nA) Small-Signal Diode • vD ≡ Bias Voltage • iD ≡ Current through Diode. iDis • Negative for Reverse Bias • Positive for Forward Bias • IS≡ Saturation Current • VBR≡ Breakdown Voltage • V≡ Barrier, or Knee, Potential Voltage

  19. 1ARectifyingDiode Data Sheet

  20. 1N914DataSheetPage-1

  21. 1N914DataSheetPage-2

  22. Diode Macro Behavior • The Knee Voltage, Vφ, is typically about 0.6-0.7 V • In the REVERSE Bias Range, the current, IS, is on the order of nA to µA, depending on the SIZE of the diode • And

  23. Diode Model  Shockley Eqn • The transconductance (vD,iD) curve on the previous slide is characterized by the SHOCKELY equation: • Where • Is ≡ Reverse Bias SATURATION Current • n ≡ emission coefficient (sometimes called the “diode quality factor”) • VT ≡ Thermal Voltage: • k ≡ Boltzmann’s constant (1.38x10−23 J/K) • q ≡ Charge on an electron (1.6x10−19Coul)

  24. Diode Model  Shockley Eqn • Note the ShockelyEqn does NOT predict Reverse-Bias BreakDown • Also when vD is Large and Negative • But we saw from the vi curves that Isis NOT constant • Also reverse Bias Currents are often much larger than Is

  25. Diode Model  Shockley Eqn • when vD is Large and Positive • At 300K VT ≈ 26 mV • if vD = 0.2V (200 mV), and n ≈ 1.5 Then • Thus the simplified Eqn is quite accurate in the FORWARD-Bias Region

  26. Diode Model  Shockley Eqn • Finally If we know iD & IS then we can solve the ShockelyEquation for vD • Note that is eqn is NOT defined for Negative Diode currents and thus applies only to the Forward Bias Region • For n = 1.5, Is = 25 µA >> iD = linspace(0,1000,500); % in mA >> vD = n*VT*log(iD/Is +1); >> plot(iD,vD) >> plot(iD,vD, 'LineWidth', 3), grid, xlabel('iD (mA)'), ylabel('vD (mV)'), title('vD by SchockelyEqn')

  27. Example: Exercise 10.2 • Consider a diode under Fwd-Bias so that this Eqnapplies: • In this case • VT = 26 mV • n = 1 • Find ∆vD so that the current Doubles: • By Fwd Bias eqn • Cancelling Is and dividing the exponential

  28. Example: Exercise 10.2 • Taking the ln of both sides of the last eqn • Thus • Then • Recalling Values for n & VT • Next, Find ∆vD so that the current increases 10X • In the above eqn replace 2 with 10

  29. ZENER Diodes • “Zeners” exploit the reverse-bias Break-Down to effect Voltage Regulation • A typical vi curve • Vz is specified explicitly • The Rev-Bias Brk-Dwn portion of the vi curve is designed to be as VERTICAL as possible • Ckt Designers use Zeners to Regulate (or PIN) a voltage point at certain level

  30. Zener Diode Voltage Regulation • A Typical ZenerCkt • A Zener diode is used in this circuit to regulate the voltage of the current supply provided by V+ to the desired Vref voltage required by this IC circuit. The small size and low cost of the Zener (compared to other techniques, such as a linear regulator or reference chip) make it ideal in this type of application. • Note that This solution would NOT work in an application with a very high V+ (forcing the device to dissipate more than a few watts). V “Pinned at Vref

  31. Source-Resistor vs Diode LoadLine • When We analyzed LINEAR DC Circuits, we arrived at Linear-Algebra Equations • i.e.; n-Eqns in n-Unknowns • Now the Diode vi curve is highly non-Linear, so the previous methods do NOT apply • The NONlinear problem can be solved NUMERICALLY (e.g. MATLAB fzero) • OR it can be solved GRAPHICALLY using so-called Load-Line Analysis • IF the powering ckt is LINEAR

  32. Digression: LINEAR Devices • V-Source: • I-Source: • Resistor: • Capacitor: • Inductor:

  33. Source-Resistor-Diode LoadLine • The simplest LoadLine analysis is a SERIES Circuit with • A Power Source (usually Voltage) • A controlling element (in this case a diode) • A Resistive Load • A pictorial Representation • By ohm & KVL • We need to find iD and vD

  34. Source-Resistor-Diode LoadLine • From the KCL eqn Notice for the Resistor • If iD=0, then vD = VSS • If vD=0, then iD= VSS/R • Plotting these two (vD,iD)points on a vD-iD curve produces a STRAIGHT-line that describes the Resistor Behavior • The Diode Curve can plotted on top of the Resistor curve • The Crossing Pt is the solution, or Operating Point

  35. Constructing the LoadLine • Recall the the KCL Eqn: • Taking iD as the depenent Variable • The above Eqn is a straight line • Need only Two Points to construct the circuit operating line (load line) so makea “T-Table”

  36. LoadLine graphic Conceptually (Also Called Quiescent, or Q, Point)

  37. Load Line Example • Consider Ckt • For the Diode Use the ShockelyEqn in Fwd Bias with • IS = 2x10−14 amps • n = 1.5 • Plot Load-Line and Diode Curve on Same Graph yields the operating point 8.3 Ω 1.5 V

  38. LoadLine Example  Q-pt ≈43 ≈1.15

  39. Check Answer by MATLAB • MATLAB Code • MATLAB Results • Thus the Graphical Estimate is quite good for the Q Point. % Bruce Mayer, PE % ENGR43 * 07Jan12 % LoadLine_Example_120107.m % Is = 2E-14 % Amps n = 1.5 vD = linspace(0,1.2,500); % 0-1.2V iD = Is*(exp(vD/(n*VT)-1)); % in Amps R = 8.3; % ohms Vss = 1.5 % Volts vR = [0, 1.5] iR = [Vss/R, 0] % plot in mA plot(vD, 1000*iD, vR, 1000*iR, 'LineWidth',3), grid,... xlabel('vD (volts)'), ylabel('iD (mA)'), title('LoadLine Analysis') % % Solve Numerically as check % fcn to Zero Zfcn = @(x) -x/R+Vss/R - Is*(exp(x/(n*VT)-1)) vDQ = fzero(Zfcn,1.1) iDQma = 1000*(-vDQ/R+Vss/R) vDQ = 1.1461 iDQma = 42.6349

  40. Zener V-Reg Load Line Analysis • A regulating Circuit • By KVL • Solving for iD again yields the LoadLine • Note that the ZenerLoadLine has a NEGATIVE y-intercept • The LoadLine T-table

  41. Example 10.3  ZenerReg • Analyze this Ckt for • VSS,lo = 15V • VSS,hi = 20V • R = 1 kΩ • Could find Zener Diode vi curve from the Data Sheet

  42. Example 10.3  ZenerReg

  43. Check Sensitivity of Zener LL • Find • Thus, for example, a 4V change in the Input, VSS, results in only a 0.4V change in the OutPut, vo • Most REAL Zeners have much STEEPER Down-Slope than that shown in the Book, so they have much BETTER output Sensitivity

  44. Complicated Circuit LL Analysis • Any LINEAR Circuit, no matter how complicated allows Diode LoadLine Analysis to determine the Q-Point • Recall that ANY linearckt can be “Thévenized” into a V-src and Series resistance or impedance • Thus to use the LL on this type of Ckt, simply disconnect the Diode, Thévenizethe LINEAR ckt-fragment and then reconnect the Diode

  45. Complicated Circuit LL Analysis • The Thévenization process concept • Then by Ohm & KVL (ClockWise current) as before • Put into y = mx+b form to produce the LoadLine (iD is dependent variable) • Now can apply the normal LoadLine Methods

  46. Example: Thevenization • Given Ckt • Find Q-point Given Zener vi Curve • First Redraw • Now Detach the NONlinear element (the Diode) and Thévenize ←VT ←RT

  47. Example: Thévenization • For VT have simple Voltage-Divider • Since have INDEP Src find RT by Source DeActivation • Setting 24V Src = 0 • Now ReAttach Diode for LoaLineCkt ←VT ←RT

  48. Example: Thévenization • Then KVL on the ThévenizedCkt • Then the T-Table • Next Draw this LoadLine on the Same Graph as the Zener vi Curve • The Q-Point is then the Intersection of the Line and Curve • See next slide −

  49. Example: Thévenization • Thus the Operating, or Q, Point for the ThevenizedCkt • vD = −10 V • iD = −10 mA

  50. Example: Thévenization • Also Find the ORIGINAL Source Current • Note that vL = −vD = +10V • Using KCL and Ohm Find • Then the Source Power

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