Look Up Machine Mid Semester Presentation

1. הטכניון - מכון טכנולוגי לישראלהמעבדה למערכות ספרתיות מהירות הפקולטה להנדסת חשמל Look Up MachineMid Semester Presentation Chanit Giat Rachel Stahl Instructor: Artyom Borzin

2. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Suggested Improvements : • 2 input FIFO’s • 2 decoders • Pipelining decoded instructions • Parallel access to Bit Map and UTCAM • Reliability: • 96 bit representation of data • ‘delete’ and ‘set attr.’ access to Bit Map

3. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Dividing the machine: • The machine will be divided into 2 main stages: up to decoding, and from the execution. • The 2 stages will be separated by a FIFO, which will schedule the flow through the machine.

4. Input FIFO 0 Decoder 0 VBF 0 F I F O DBM Output FIFO CRC Input FIFO 1 Decoder 1 VBF 1 High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות New Block Diagram:

5. SOT & !wrfull(1) 1 0 !SOT !SOT SOT & !wrfull(0) High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Doubling the front end of the machine: • Modifying the Data Stream Controller, so it passes the transactions to the FIFO’s – one at a time: • This decision will mainly improve the handling of 2 following “long” ‘search’ commands.

6. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות OOO considerations: • At the beginning, separating the ‘search’ command from the others was considered, but abandoned: • Command dependencies: it may work sometimes, but the results will not fit the order in which the commands were sent. • A better performance gain from decoding ‘search’ commands in parallel to each other, than in parallel to other commands.

7. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Doubling the front end of the machine (cont.) • There are 2 options regarding the CRC module: • Doubling the HW • Space • Frequency • Scheduling the access to the module • Effort

8. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Doubling the front end of the machine (cont.) • Scheduling decoded instructions: additional HW will pass instructions to the DBM Input FIFO from one decoder at a time: • The decision is almost identical to the one before the input FIFO’s:

9. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות !Wr_done 0’ dec0_rdy & !fifo_full Wr_done 1 0 !dec0_rdy !dec1_rdy 1’ dec1_rdy & !fifo_full Wr_done !Wr_done FIFO scheduling FSM

10. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות DBM Input FIFO • The FIFO schedules the transition between the 2 parts of the machine. • The packets are different for each instruction: The longest packet is 133 bits long. • Additional HW will be needed to divide the signals to the right c-level blocks, at the Issue Logic.

11. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות DBM Input FIFO • 133 bits FIFO – possible problems: - space - frequency • Possible solution: • Transferring the fields in 2/3 stages, each 64 bits long • Need for extra HW to reorganize the fields.

12. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Search command flow – present algorithm Calculate 64bit CRC value for the received data Query CAT for entry with [Site#, CRC] Yes No Found Return PATH and Status Find the next empty place in CAT Insert new record to CAT and AT Successful No Yes Return Error Return PATH and Status

13. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Valid_index ADD Block Bit Map Unit Index Register ack exunit Parallel access to Bit Map and UTCAM

14. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Search command flow – new algorithm Calculate 64bit CRC value for the received data Find the next empty place in CAT Query CAT for entry with [Site#, CRC] Yes No Found Return PATH and Status Insert new record to CAT and AT Successful No Yes Return Error Return PATH and Status

15. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Reliability Issues: • Will be implemented if schedule allows. • Suggested changes do not contribute to throughput. • Delete and Set_Attr access to valid indexes can be under the OS responsibility.

16. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות schedule • 1 week: tools, study code • 4-6 weeks: design (best case) • 2 weeks: debug + performance check

17. CID – 5 bits. AsIs – 32 bits. Site – 32 bits. Path – 21 bits. ttl, weight – 16 bits each. CRC – 64 bits. Search: CID, AsIs, site and CRC – 133 bits. Set_Attr: CID, AsIs, path, ttl & weight – 90 bits. Delete: CID, AsIs & path – 58 bits. Count Free & Init: CID & AsIs – 37 bits. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות The fields transferred by the decoder:

18. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Dividing the fields into 70-bit wide FIFO: • Search: • CID + site : 37 bits. • CRC: 64 bits. • AsIs: 32 bits. • Set_Attr: • CID + path + ttl + weight : 58 bits. • AsIs: 32 bits. • Delete, count free & init can be transferred in one row in the FIFO.

19. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Valid_index ADD Block Bit Map Unit Index Register ack Parallel access to Bit Map and UTCAM • Initiation: when initiating the Bit Map Table, init the register to 21’h0. • ADD block: • Reads the register, and tries to write to the AT/CAT. • If unsuccessful : nothing happened… • If successful : sets the ack bit. • Bit Map Unit: when receiving ack: • Clears the valid bit. • Marks the current index as taken. • Looks for the next free index, and updates the register. • Sets the valid bit.