Project Mid Semester

1. Project Mid Semester 11.1.2011 Implementing a compressor in software and decompression in hardware Presents by - Schreiber Beeri YavichAlon • Guided by – Porian Moshe

2. Reminder Gym Control Room Gym Compressed data (Wireless) ❤ ❤ 142 132 ❤ ❤ 170 79 ❤ ❤ 130 127

3. Reminder (Cont.) • Transmitter Compresses the data • Receiver extracts and displays the data

4. TOP architecture

5. FPGA – Cyclone II Packet TX Host Matlab RAM MUX Message Encoder UART TX TX 115,200KBit/sec REGISTERS RX Packet RX UART RX DEC RAM Message Decoder Sys. Clk PLL Ext. Clk Mem Write CRC Reset D’ bouncer Sys. Rst Ext. Reset Mem Read Arbiter VGA Display Display Controller SDRAM Controller RunLen Decoder IS42S16400 SDRAM VESA 800x600 Implemented, not integrated Done Not Implemented Update Required

6. Micro architecture

7. VGA Display Matlab CRC_ERR VALID Line legend MSG_OK 1 bit VALID REQ Message Decoder RAM Controller 8 bits RD_adress 10 bits 16 bits n_pix RGB 22 bits Display Controller WR_addr WREN DATA Num Pixels 40MHz RAM UART UART RXD UART RXP REG Controller DATA EN DATA DATA FIFO (dual clock) Data&Valid UART TXD from UART TX REQ DEC CheckSum & Valid CheckSum TYPE REG Addr REG Len REG Type COL_EN COLOR CRC_ERR FROM MSG_DEC RunLen Decoder DATA DATA REGISTERS MP REGS CRC Status REG CRC STATUS RX_RDY to MEM READ DATA DATA_RDY from MEM READ REQ Mem Write RESET Status EN UART TXD to UART TX REP RX_RDY from MEM READ DATA_RDY to MEM READ Addr SDARM ACK DATA REQ SDRAM Controller COLOR UART TXP DATA Arbiter Mem Read Data & Control Data & Control EMPTY REQ REQ VALID ACK TX PACK FIFO DATA & Valid DATA 40MHZ (VESA) Adress Reset Debouncer PLL Resets 50MHZ 133MHZ (SDRAM) VALID REQ FULL

8. Method of Operation • Project Directory Structure • The work method established in the project was assisted with these tools: • SVN • Code review • Coding Guidelines • Excel assignment file

9. Excel assignment file

10. UART’s Test Bench UART Comparator RAM UART TX UART RX Message Pack Decoder Message Pack Encoder UART Generator CheckSum FIFO CheckSum This will be shown using Matlab and DE2 board

11. Maximum Current Frequency • According to Quartus Timing Analyzer: 150MHz, in this implementation Signal route through FPGA Logic Pin

12. Current Implemented IPs • UART Rx, Tx • Noise-proof • 5-8 Data Bits • Enable / Disable Parity Bit • Odd / Even Parity Bit • Parity & Stop bit Error • System clock and UART transmission clock is set by generic parameter Start Bit 5-8 Data Bits Parity Bit (Optional) Stop Bit

13. UART TX’s FSM fifo_empty IDLE Shift Register reset 1 1 1 1 1 1 0 1 0 0 0 1 1 1 0 1 0 0 0 1 0 0 1 1 1 1 0 1 0 0 0 1 0 1 1 1 1 1 0 1 0 0 0 1 1 1 1 1 1 1 1 1 0 1 0 1 1 1 1 1 1 1 0 1 0 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 dout not fifo_empty Data – A2 Hex pos_cnt = databits + paritybit + 1 REG DATA TX fifo_Din_Valid

14. Current Implemented IPs • Message Pack Encoder • Encodes a message from registers, RAM and CRC block • Generic block size • Message Pack Decoder • Decodes a message into registers, RAM, and compares CRC • Generic block size

15. Current Implemented IPs • CheckSum Block • Calculates Signed / Unsigned Checksum • Generic input and output size • Comfortable handshake data_valid reset_checksum req_checksum checksum_valid

16. Current Implemented IPs • Generic MUX • Generic input, selectors • Generic Decoder • Generic selectors

17. Current Implemented IPs • Generic RAM • Generic input / output size (Under Development) • Generic FIFO • Generic FIFO size, data width • SDRAM Controller • IS42S16400 Model Written in pure VHDL. Independent  in the FPGA’s vendor

18. RAM – Different Implementations • First Implementation: Resources: 8209 DFF 8192 MUX And more…

19. RAM – Different Implementations • Current Implementation: Din_valid Dout_valid Addr_in Addr_out_valid Addr_out Data_out Data_in Resources: 5 DFF 4 MUX 1 Decoder 2 Sync RAM

20. Current Implemented Simulation Models • UART Generator • Generates UART transmission from text file • Generic UART parameters: • Enable / Disable Parity bit • Even / Odd parity bit • Various transmission rates • Generic delay between files transmission • UART Comparator • Compares received UART transmission to text file

21. Simulation Method • Various Macro (DO) files, each one execute the simulation with different generic parameter. • Validate wave against expected signals • Automatic software validation of actual data against expected data

22. UART Simulations: One Kbyte data transfer has been simulated

23. UART Simulations (Cont.): One Kbyte data transfer has been simulated

24. Documentations • Done: • SDRAM Controller • UART RX, TX • To do: • MessagePack + Checksum • RAM • FIFO • MUX • Decoder

25. Schedule Done Done Done Done Done Partial Done Done Done

26. Schedule