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FE8113 ”High Speed Data Converters”

FE8113 ”High Speed Data Converters”. Part 2: Digital background calibration.

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FE8113 ”High Speed Data Converters”

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  1. FE8113 ”High Speed Data Converters”

  2. Part 2: Digital background calibration

  3. Papers 3 and 4:J.P.Keane et.al: “Digital Background Calibration for Memory Effects in Pipelined Analog-to-Digital Converters”, IEEE Transactions on Circuits and Systems I: Regular Papers : Accepted for future publication, Volume PP,  Issue 99,  2005 pp 1-15J.Ming, S.Lewis: “An 8-bit 80-Msample/s Pipelined Analog-to-Digital Converter With Background Calibration”, IEEE Journal of Solid-State Circuits, Vol. 36, No. 10, October 2001, pp 1489-1497

  4. This week’s funny picture: ”Nervous moment” by G.I.Joe

  5. J.P.Keane et.al: “Digital Background Calibration for Memory Effects in Pipelined Analog-to-Digital Converters” Outline: Memory errors can occur in the stages of a pipeline ADC due to several effects. This paper describes the sources of such memory effects and the impact they have on ADC performance. Then, two new algorithms for digital calibration of memory effects are proposed.

  6. J.P.Keane et.al: “Digital Background Calibration for Memory Effects in Pipelined Analog-to-Digital Converters” Introduction to the pipeline ADC and notation Stage i output: Stage transfer function Total ADC output Everything ideal

  7. J.P.Keane et.al: “Digital Background Calibration for Memory Effects in Pipelined Analog-to-Digital Converters” Sources of memory effects Capacitor dielectric absorption/relaxation effect: 1) Charge cap to VC=Vinit 2) At t=0, discharge by short until t=t0 3) Allow the capacitor to float until t=tf Charge gather back from dielectric to plates Ideal pipleline SC-stage Normalized values

  8. J.P.Keane et.al: “Digital Background Calibration for Memory Effects in Pipelined Analog-to-Digital Converters” Sources of memory effects - Add model for cap dielectric absorption/relaxation memory effect 1) At t=(k-0.5)T: Cin and Cf charged to VDASC(kT-T/2) and Vi+1(kT-T/2) 2) During φ1: Cin and Cf connected to Vi and ground, voltage => Vi(t) 3) At t=kT: Switch opens, capacitor terminals float during φ2 => Relaxation voltage VCin=γVDACS(kT-T/2) and γVi+1(kT-T/2) at Ci and Cf during φ2 - Additional charge on Cin transferred to Cf - Net additional charge on Cf: CfVCf+CinVCin - Set up linear charge transfer equation for residue output - Normalized:

  9. J.P.Keane et.al: “Digital Background Calibration for Memory Effects in Pipelined Analog-to-Digital Converters” Sources of memory effects - Incomplete stage reset effects - T is chosen long enough to allow settling to the required accuracy of the conv - Incomplete settling in φ2 => errors in interstage gain Gi and DASC gain Ki - Can be corrected using conventional calibration techniques - Incomplete settling in φ1 causes memory-effects - Can not be corrected using conventional calibration techniques - Linear settling model - Phase φ1 from t=kT-T/2 to t=kT - γin and γf are settling time constants of Cf and Cin - At the end of φ1 -Assuming Vcf(kT+T/2)=Vi+1(kT+T/2), VCin(kT+T/2)=VDASC(kT+T/2)

  10. J.P.Keane et.al: “Digital Background Calibration for Memory Effects in Pipelined Analog-to-Digital Converters” Sources of memory effects - Incomplete stage reset effects - Assuming VCf(kT+T/2)=Vi+1(kT+T/2), VCin(kT+T/2)=VDASC(kT+T/2) - Changed coefficient for Vi(kT) - Gi=(1-γf)+((1-γf)Cin/Cf - The gammas, and hence the gain is dependant on previous output and DASC input.

  11. J.P.Keane et.al: “Digital Background Calibration for Memory Effects in Pipelined Analog-to-Digital Converters” Sources of memory effects - Opamp sharing effects - Subsequent stages work in opposite phases and opamp is only needed in the amplification phase => two and two stages share one opamp. Memory effects due to input parasitic capacitance and limited gain - Voltage at the end of amplifying phase: Vm=-Vout/a - At the end of φ2: Vout=Vi+1(kT-T/2) => Vm=-Vi+1(kT-T/2)/a - φ1: Cp injects CpVm at summing node of second stage generating Vout=Vi+2(kT) - Transfer function of stage 2 during φ1 - Normalized form

  12. J.P.Keane et.al: “Digital Background Calibration for Memory Effects in Pipelined Analog-to-Digital Converters” Sources of memory effects - Opamp sharing effects - φ2: Cp injects CpVm at summing node of first stage generating Vout=Vi+1(kT+T/2) - Transfer function of stage 1 during φ2 - Normalized form - Output of stage 1 depends on previous output of stage 2

  13. J.P.Keane et.al: “Digital Background Calibration for Memory Effects in Pipelined Analog-to-Digital Converters” Sources of memory effects - Opamp sharing effects - Only odd stages have memory effect - Even stages have an interstage gain error - Model for opamp sharing memory effects - Can be constrained within one stage - Equivalent model for ADC transfer function given when:

  14. J.P.Keane et.al: “Digital Background Calibration for Memory Effects in Pipelined Analog-to-Digital Converters” Linearity error due to memory effects First: summarize the memory effects described in stage transfer function γi and δi correspond to memory effects γfand γin resp. Can often be assumed equal for mentioned memory effects

  15. J.P.Keane et.al: “Digital Background Calibration for Memory Effects in Pipelined Analog-to-Digital Converters” Linearity error due to memory effects - Now, we can find nonlinearity due to memory effects by tracing recursively from the final stage output (XN(z)) to the output signal of the input SHA (X0(z)). - First terms is linear filtering, second term is non-linear error, containing a weighted sum of past stage decisions. - Past decisions are correlated with the input.

  16. J.P.Keane et.al: “Digital Background Calibration for Memory Effects in Pipelined Analog-to-Digital Converters” Simulation of memory error effect on INL in otherwise ideal ADC 12b LSB-level, 95% of full scale sinus in a) γi and δi = 0.005 for first stage only b) γi and δi = 0.005 two first stages c) γi and δi = 0.005 all stages Memory error dominated by second stage

  17. J.P.Keane et.al: “Digital Background Calibration for Memory Effects in Pipelined Analog-to-Digital Converters” Background calibration for memory effects A) LMS-method using parallel ADC

  18. J.P.Keane et.al: “Digital Background Calibration for Memory Effects in Pipelined Analog-to-Digital Converters” LMS-method using parallel ADC - Parallel reference ADC operating at 1/M of main ADC speed - Ref. ADC is low-power, low-speed high linearity (e.g. delta-sigma) - Error-signal e[n] is an estimate of main-ADC nonlinearity - Used in a negative feedback loop that adjusts the calibration to minimize the mean-square value of the error - Digital calibration block performs: - Where are estimates of the ideal weights wi LMS-algorithms gives:

  19. J.P.Keane et.al: “Digital Background Calibration for Memory Effects in Pipelined Analog-to-Digital Converters” LMS-method using parallel ADC - Output with memory effect rewritten: - Since Q is unknown, appropriate expression to correct for mem.errors: - To find the estimation coefficients for wi,k we apply the LMS-algorithm - µi,k is a small number chosen as compromise between tracking speed and steady-state variation

  20. J.P.Keane et.al: “Digital Background Calibration for Memory Effects in Pipelined Analog-to-Digital Converters” LMS-method using parallel ADC - In direct form, i+1 coefficients are needed for stage i. - Total number of coefficients for N-stage ADC: - Since later stages contribute very little, only L first stages are calibrated - Removing quantization terms similar to the previous example yields:

  21. J.P.Keane et.al: “Digital Background Calibration for Memory Effects in Pipelined Analog-to-Digital Converters” LMS-method using parallel ADC - Now the number of coefficients is reduced to: - Drawback: Converged value of coefficients will be dependent on input PDF. - Good calibration relies on the input varying over many possible levels to provide different decisions for all di[n] and hence estimation of all wi - Input signal waveform with uniform distribution over full signal range is preferable. - Convergence time is fastest when input signal is correlated - Input signal waveform with discrete distribution is preferable.

  22. J.P.Keane et.al: “Digital Background Calibration for Memory Effects in Pipelined Analog-to-Digital Converters” Background calibration for memory effects B) Calibration using DAC dithering and stage redundancy

  23. J.P.Keane et.al: “Digital Background Calibration for Memory Effects in Pipelined Analog-to-Digital Converters” Calibration using DAC dithering and stage redundancy Interstage gain estimated by randomly dithering DASC input Stage input estimate: Estimate of mi=1/Gi Estimate of error in coefficient : Scale of dither signal determines amount of information about errors in present in Limits tracking speed

  24. J.P.Keane et.al: “Digital Background Calibration for Memory Effects in Pipelined Analog-to-Digital Converters” Calibration using DAC dithering and stage redundancy -Extend model to include interstage error and memory effect. - Signal flow - Generally γi≈δi: - If opamp-sharing, δi=0 and:

  25. J.P.Keane et.al: “Digital Background Calibration for Memory Effects in Pipelined Analog-to-Digital Converters” Calibration using DAC dithering and stage redundancy - Stage transfer function: - In time-domain: - Then, calibration expression becomes:

  26. J.P.Keane et.al: “Digital Background Calibration for Memory Effects in Pipelined Analog-to-Digital Converters” Calibration using DAC dithering and stage redundancy -After some algebra, we get: - Where: - If the error signal is uncorrelated and spectrally white, we get: - And the coefficient update equation is given by:

  27. J.P.Keane et.al: “Digital Background Calibration for Memory Effects in Pipelined Analog-to-Digital Converters” Calibration using DAC dithering and stage redundancy In words: - The ADC error due to memory effect are proportional to the previous value of the stage residue. - Random dithering of DASC causes the mean value of the stage residue to change by Kiri[n] - Adjusting the coefficient as given forces the stage input estimate to be uncorrelated with the previous stage residue, overcoming the memory effect. - The different dither signals ri[n] must each be uncorrelated with each other.

  28. J.P.Keane et.al: “Digital Background Calibration for Memory Effects in Pipelined Analog-to-Digital Converters” Simulation results: - 6-stage pipeline ADC - 2.5b stages with 6 ADSC levels - Gi=4 - Final stage is 4b flash - When simulating dither calibrated ADC, each stage has 7 ADSC levels and 16 DASC levels to accomodate overhead needed for dither signal - Memory effect with γi=δi=0.005 in both cases. - Mean interstage gain error of -1% also introduced - Calibration of first five stages

  29. J.P.Keane et.al: “Digital Background Calibration for Memory Effects in Pipelined Analog-to-Digital Converters”

  30. J.P.Keane et.al: “Digital Background Calibration for Memory Effects in Pipelined Analog-to-Digital Converters”

  31. J.P.Keane et.al: “Digital Background Calibration for Memory Effects in Pipelined Analog-to-Digital Converters” - LMS algorithm gives best results - LMS algorithm has fastest tracking - Dither algorithm is independent of input signal statistics - Dither algorithm does not require highly linear refrerence DAC.

  32. J.Ming, S.Lewis: “An 8-bit 80-Msample/s Pipelined Analog-to-Digital Converter With Background Calibration” Outline: An 8-bit 80Msample/s pipelined ADC uses monolothic background calibration to reduce the nonlinearity caused by interstage gain errors

  33. J.Ming, S.Lewis: “An 8-bit 80-Msample/s Pipelined Analog-to-Digital Converter With Background Calibration” Introduction and review - Stage with k-bit ADSC, k-bit DASC and SHA with gain G. - Internal resolution greater than output resolution to introduce redundancy - Overcome effects of comparator and SHA offset. - Accuracy limitations stem from linearity of DASC and gain accuracy of SHA.

  34. J.Ming, S.Lewis: “An 8-bit 80-Msample/s Pipelined Analog-to-Digital Converter With Background Calibration” Introduction and review - Conventional SHA - With infinite gain and perfect capacitor matching G=2 - Gain error due to mismatch, limited gain and incomplete settling - Proposed algorithm corrects all these.

  35. J.Ming, S.Lewis: “An 8-bit 80-Msample/s Pipelined Analog-to-Digital Converter With Background Calibration” Interstage Gain-Error Compensation - Interstage gain-error transformed to ADC gain error by moving GE to output of DASC - Effect is eliminated in model if VR1=VR2/GE - Proposed algorithm calibrates gain error by adjusting DASC reference voltages during the normal operation of the ADC

  36. J.Ming, S.Lewis: “An 8-bit 80-Msample/s Pipelined Analog-to-Digital Converter With Background Calibration” Interstage Gain-Error Compensation - RNG produces random, while calib signal N[i]=±1 for all I - Converted with 1-bit DAC and added to stage input - Multiplied by GD1 and quantized at the back end ADC2 - DAC1 reference Vn digitized by slow-but-accurate ADC - Result is multiplied with N[i] and subtracted from ADC2 output - Producing error signal εi - Error signal εi is multiplied with N[i], scaled by µ and accumulated. - Accumulator output control DAC2 to set reference voltage VR1

  37. J.Ming, S.Lewis: “An 8-bit 80-Msample/s Pipelined Analog-to-Digital Converter With Background Calibration” Interstage Gain-Error Compensation - Accumulator input averages to N2 - The N·Vin product part averages to zero since they are uncorrelated - If slow-but-accurate ADC and ADC2 are ideal: - To set the average accumulator input to zero, the loop adjusts VR1_average until εc_average= 0, which gives:

  38. J.Ming, S.Lewis: “An 8-bit 80-Msample/s Pipelined Analog-to-Digital Converter With Background Calibration” Interstage Gain-Error Compensation - In practice, random fluctuation occur around VR1_average - Can be made arbitrarily small by reducing step-size µ - Also assures stability of the loop - Injection of calibration signal must not saturate ADC2 - Vn≈VR2/4 chosen along with GD1≈1 - Amplitude is half the correction range of ADC1, leaving headroom for comparator offset etc

  39. J.Ming, S.Lewis: “An 8-bit 80-Msample/s Pipelined Analog-to-Digital Converter With Background Calibration” Effect of non-linearity in the back-end ADC - Back-end measure the calibration signal injected into first stage - Comparator offset - Digital redundancy and correction - Input-referred offset - Has little effect on loop convergence as it is whitened by N[i] - Gain-error in first backend interstage amplifier - G2≠2

  40. J.Ming, S.Lewis: “An 8-bit 80-Msample/s Pipelined Analog-to-Digital Converter With Background Calibration” Effect of non-linearity in the back-end ADC - Gain error in first backend interstage amplifier. - Case 1: Vres[i] has a value such that adding cal.sig. does not change D2 - The calibration signal appears entirely in VG2 - Change in VG2: N[i]·1/2·LSB·G2 - Case 2: Vres[i] has a value so that adding cal.sig. changes D2 one code - The noise appears in combination of D2 and G2 - Change in VG2: -N[i]·1/2·LSB·G2 - Combining the two cases equal cancels out average error caused by G2 - Given by shaded regions in figure - Calibration is only done when the signal is in these regions.

  41. J.Ming, S.Lewis: “An 8-bit 80-Msample/s Pipelined Analog-to-Digital Converter With Background Calibration” Prototype implementation - 0.5µm CMOS - 1.5b stages - Calibration of two first stages - VR1 adjusted with respect to VR2 - Delta sigma slow-but-accurate-ADC - 7b DAC for reference voltage control - µ=2-21 - 0.25pF sampling cap, 54dB open-loop gain, 0.1% settling

  42. J.Ming, S.Lewis: “An 8-bit 80-Msample/s Pipelined Analog-to-Digital Converter With Background Calibration”

  43. J.Ming, S.Lewis: “An 8-bit 80-Msample/s Pipelined Analog-to-Digital Converter With Background Calibration”

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