Implementation Issues for Channel Estimation and Detection Algorithms for W-CDMA

1. Implementation Issues for Channel Estimation and Detection Algorithms for W-CDMA Sridhar Rajagopal and Joseph Cavallaro ECE Dept.

2. Contents • Introduction • W-CDMA • Channel Estimation and Detection • DSP Implementation • ASIC Implementation • Other Current Projects • Future Work

3. The CDMA Research Group • We cover the entire (spread) spectrum! • Algorithms • Implementation issues D M

4. Implementation Issues • Important because • Real-time • Low Power • Mobility /Size • DSPs • Signal Processing Communications • ASICs / FPGAs • Speed / Size

5. W-CDMA • CDMA : Code Division Multiple Access • W-CDMA : Wideband CDMA (5 MHz) • Next Generation Communication Systems • Integrating Multimedia Capabilities • QoS /Multi-rate Services • Higher Data Rates 2048,384,144 Kbps

6. Uplink - Async, Multiuser Direct Path Noise + MAI Base Station Reflected Paths User 1 User 2

7. Downlink - Sync, Single User Direct Path Reflected Paths Noise + MAI Base Station User 1 User 2 User 1

8. Determining the Channel • Channel Estimation • Need to know the Channel for proper detection • Delays and Amplitudes : Multiuser/path • Send sequence of known bits (Pilot / Preamble) • 2 types • Code Multiplexed with Data • Time Multiplexed with Data • Detection • Use knowledge of channel for detection of Data bits

9. W-CDMA Standards • Not fixed yet…... • Uplink • Channel Estimation - Time Multiplexed • Multiuser Detection • Downlink • Channel Estimation - Common Pilot • Detection : Rake Receivers/ Equalizers

10. Channel Estimation • Uplink • Time Multiplexed • Maximum Likelihood • Subspace • Downlink • Continuous • LMS Based Adaptive

11. Multiuser Detection Optimal Sub-optimal MLSE (Viterbi) Linear Interference Cancellation Neural Network • MAI Whitening • Decorrelating • MMSE • Serial SIC • Parallel PIC

12. Base-Station Receiver Antenna Multiuser Detector Data Demux Decoder Demodulator EstimatedAmplitudes&Delays Pilot ChannelEstimator

13. y1 Channel Decoder Multi- User Detector Matched Filter User 1 d1' Channel Encoder User 1 d1 Spreading AWGN y2 User 2 d2' Matched Filter Channel Encoder User 2 d2 Spreading + R(t) yK Matched Filter User K dK' Channel Encoder Demux Spreading User K dK Channel Estimator CDMA Uplink System

14. Maximum Likelihood Channel Estimation • Send a time-multiplexed Preamble (Pilot). • Channel properties extracted • Compare with known pilot and estimate. • Keep estimate for remaining data bits (static). • Repeat preamble every frame, if no tracking.

15. The Maximum Likelihood Algorithm • Compute the correlation matrices • Compute the channel estimate • Calculate the noise covariance matrix K. • Calculate the channel impulse response vector z. • Extract the ampitudes and delays using least squares fit.

16. The ML Algorithm Complexity • Complex-Real Dot Product. • Complex-Real Matrix Product. • Complex -Real Product. • Real Square roots. • Solving quadratic equation for least squares fit. • Critical code : Matrix-vector / Dot Product Offline Assuming Unity Noise Covariance

17. Differencing Multistage Multiuser Detection • Based on the principle of Parallel Interference Cancellation (PIC) • Cross-correlation information used to remove interference of other users • Repeated iterations for convergence • Differencing techniques to improve performance

18. The Differencing Multistage Detector • Split the cross correlation matrix into lower, upper and the diagonal matrix. • Calculate impulse response • x is called the differencing vector.

19. Multistage Detector Complexity • Matrix Multiplication: • Computed only once for one frame • Dot Product: • Computed iteratively • Critical code: Dot Product

20. TI Tools Used • Evaluation Modules (EVM) for C6201 and C6701 fixed and floating point DSPs • 64 KB each internal program & data memory • 256 KB SBSRAM, 8 MB SDRAM (external) • C Compiler ver 3.0 from Code Generation Tools • Code Composer ver 4.02 for profiling

21. DSP Implementation: Channel Estimation • Floating point implementation found more feasible due to matrix inversions and square-roots. • Code optimized for the DSP • Use of Specialized approximate instructions • Approximate reciprocal square roots • Approximate reciprocals • Use of Assembly Code for critical part. • TI's C67 floating point benchmarks for Matrix-Vector Multiplication & Dot Product • Data Memory requirements for Channel Estimation

22. Use of specialized instructions and assembly code on C6701 DSP 140 C6701: Original C6701: with Intrinsics 120 C6701: with Assembly 100 10% improvement 80 Execution time(in milliseconds) --> 60 40 100% improvement 20 0 0 5 10 15 Number of users --> Approximate Instructions & Assembly L = 150, P =3, N= 31, SNR = 5dB, SINR = -10 dB

23. Data Memory Requirements Data to be placed in External memory 6 130

24. DSP Implementation: Multistage Detection • 16-bit Fixed Point C Code • Code optimized for the DSP • Use of Assembly Code for critical part • TI's C62 fixed point assembly benchmarks for Dot Product • Data memory requirements for Multistage Detection

25. Data Memory Requirements Data can be placed completely in Internal memory

26. Users:K=15 SNR=6dB 4 x 10 14 12 Conventional Method Differencing Method 10 8 Number of Flops 6 4 2 0 1 2 3 4 5 6 7 8 Total Number of Iterations Flops Count 2X speedup for a three-stage detector conventional differencing

27. SNR=10dB Window Size=12 350 300 Conventional Method Differencing Method 250 200 MAX BIT RATE PER USER (kb/s) 150 100 50 8 9 10 11 12 13 14 NUMBER OF USERS Real-Time Requirements Real-Time capability by C6201 DSP 12users 150kb/s

28. Trends in Recent DSPs • More internal memory and higher clock speeds • C6203 : 512 KB data, 384 KB program, 250 MHz • useful for uplink channel estimation algorithms. • Specialized Blocks in the DSP Core. • Viterbi decoding in C54. • Lower Voltage operation • 1.2 V in C5402 , useful for saving power consumption in the mobile.

29. ASIC Implementation • MOSIS Tiny-Chip (40-pin DIP) • 8 synchronous users • 12-bit fixed point implementation • 6000 transistors • 1.2 m CMOS technology • 190kb/s for each user (@12.5MHz) • 3-stage cascade delay < 15 s

30. Advantages of ASICs • Highly paralleled instructions: 4 RISC IPC (instructions per cycle) • accumulating while shifting, loading and storing • recoding while loading • Application specific architecture • faster I/O • smaller on chip memory • smaller ALU

31. REG A L U SHIFT RECODER Control Logic (L+L’)A Chip (Single Stage) Architecture Internal signals External signals

32. Chip Layout 2.0 mm Soft Decisions Recoding logic Cross-Correlation 12-bit ALU

33. The Actual Chip Photograph

34. Matched Filter Output Detector Output Sout Sout Sout Sin Sin Sin Hin Hout Hin Hout Hin Hout Output Valid Hand Shaking Fin Fout Fin Fout Fin Fout Load Load Load CLK CLK CLK 1/2 1/2 1/2 Load R Clock 3-stage Cascade Mode

35. System Timing Final Output Load R 1st Stage 2nd Stage 3rd Stage

36. 10100000 00100000 00100000 Interference Cancellation

37. Scalable ASIC Design Xilinx FPGA XC4000: 500k gates, 96MHz

38. DSP-ASIC Comparison • TI’s ‘C54xx: General purpose DSP core + ASIC

39. Other Current Projects • Simulation Testbed • Entire Chain of Algorithms • Simulink - RTW • Rapid Prototyping • Matlab to DSP • Copper Contest • Implementation of Multistage Detector using 0.15 micron Copper Technology

40. Wireless LAN Project Home Area Wireless LAN Outdoor CDMA Cellular Network High Speed Office Wireless LAN

41. Future Work • Fixed Point Implementations on DSPs/ASICs • Uplink & Downlink Algorithms • Approximations using Linear Algebra • Support Long Codes and Fading • Multistage Detector • Execution time Predictability • Increase Efficiency • GPP Comparisons : Praful, Partha, Dr.Adve • Effect of DMA and Caches