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Channel Estimation for W-CDMA on DSPs

Sridhar Rajagopal ECE Dept., Rice University. Channel Estimation for W-CDMA on DSPs. Elec 599. Organization. W-CDMA. DSPs in Wireless Communications. Channel Estimation. Aim of the 599 Project. Implementation Issues and Results. Future Architectures for Wireless systems.

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Channel Estimation for W-CDMA on DSPs

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  1. Sridhar Rajagopal ECE Dept., Rice University Channel Estimation for W-CDMA on DSPs Elec 599 SR: 599 report

  2. Organization • W-CDMA. • DSPs in Wireless Communications. • Channel Estimation. • Aim of the 599 Project. • Implementation Issues and Results. • Future Architectures for Wireless systems. • Conclusions and Future Work. SR: 599 report

  3. W-CDMA • Third Generation Communication Systems. • Multimedia Capabilities. • Multirate Services. • Quality Of Service. • Higher Data Rates. • 2Mbps, 384kbps, 144kbps. SR: 599 report

  4. DSPs in Wireless Communications • Digital Signal Processor. • Signal Processing Communications. • Features : • Low Power Consumption (1.2 V, 100 mW). • Low Cost (15$). • High Performance (100 MIPS). SR: 599 report

  5. The Wireless Channel : Multiuser, Multipath Direct Path Antenna Reflected Paths Faces Attenuation, Delays and Doppler Effects : Unknown Channel Parameters SR: 599 report

  6. At the Receiver CHANNEL ESTIMATOR DECODER DEMODULATOR DETECTOR UZ A, R SR: 599 report

  7. ML Channel Estimation • Send a Preamble. • Channel properties embedded in received signal. • Compare and estimate. • Keep estimate for remaining data bits (static). • Repeat preamble every frame, if no tracking. SR: 599 report

  8. Data Transmission in W-CDMA Packet Preamble for Acquisition Packet for Data Transmission Mobile # C4 C1 1. 2. C7 C3 C1 C2 3. C2 4. C4 5. C8 C2 : time DS-CDMA with Slotted ALOHA SR: 599 report

  9. W-CDMA- Implementation Issues • Computationally intensive algorithms. • Stringent Time, Power, Size constraints. • Pressure on existing hardware resources. • Real -time Requirements : 1ms 10ms Preamble Message 0.25 ms Random Access Burst in Slotted ALOHA SR: 599 report

  10. Aim of the 599 Project • Get a grasp of • W-CDMA. • DSPs. • Channel Estimation. • Implement ML Channel Estimation on DSPs. • Evaluate its performance (“Execution Time”). • Ways to improve the performance. • Future Architectures for Wireless Communications. SR: 599 report

  11. The ML Algorithm Complexity • Complex -Real Dot Product. • Complex-Real Matrix Product. • Complex -Real Product. • Real Square roots. • Solving quadratic equation for least squares fit. COMMON Offline Assuming Unity Noise Covariance SR: 599 report

  12. TI TMS320C6701 EVM • 32-bit Floating Point DSP at 133MHz. • VLIW Architecture (8 IPC). • 8 Functional Units ( 2 Multipliers). • 32 registers in 2 files. • 64 Kb each Internal Program and Data Memory. • External Memory. • 256 Kb SBSRAM (Static RAM : faster). • 8 Mb SDRAM (Dynamic RAM : slower). SR: 599 report

  13. Steps in DSP Implementation • Original Floating Point Code. • Remove File I/O. • Minimize use of functions. • Minimize use of temporary variables. • Pre-computed Data (Offline). • Use Specialized Approximate Instructions. • Use Assembly Code for critical part. SR: 599 report

  14. Use of Approximate Instructions L = 150, P =3, N= 31, SNR = 5dB, SINR = -10 dB SR: 599 report

  15. Use of Assembly Code L = 150, P =3, N= 31, SNR = 5dB, SINR = -10 dB SR: 599 report

  16. Comparison with UltraSPARCII • UltraSPARCII • Super-scalar • 4-way in-order • 250 MHz • VIS support L = 150, P =3, N= 31, SNR = 5dB, SINR = -10 dB SR: 599 report

  17. Joint Estimation and Detection • Improvement in performance as only subset of parameter extraction. • Improvement in detector also?. L = 150, P =3, N= 31, SNR = 5dB, SINR = -10 dB SR: 599 report

  18. Memory Issues • Data sizes do not fit in Internal memory. • Onus on Programmer. • External Memory Latencies. • Affects performance SR: 599 report

  19. Improvements in Architecture • Internal Memory. • More internal memory required - On-chip DRAMs. • Data Prefetching. • Matrix oriented operations - Prefetch Buffers. • ASIC/FPGA Support. • Offload critical computations (Viterbi Decoder in C54) • Specialized Instructions. • Array Based instructions, Complex Arithmetic. SR: 599 report

  20. Improvements in Compilers • Compiler Efficiency. • VLIW Compilers unable to extract all parallelism. • Assembly language subroutines. • Advantages of Architecture not used fully. • OS Support. • Memory Allocation by Programmer. • May not be optimal / Leads to Errors. • Compiler should assist. • Suggestions acknowledged by TI. SR: 599 report

  21. Future Architectures for Wireless • Large On-chip Memory. • Low Cost / High Performance. • Low Power Consumption. • Multiple DSPs. • GPP-DSP-Coprocessor-ASIC-FPGA. • Vector IRAMs. SR: 599 report

  22. Conclusions • Studied ML Channel Estimation on DSPs. • Effect of Approximations (1.1X). • Effect of Assembly (2X). • GPP Comparison (0.2227 X for 15 users). • Joint Estimation and Detection (2.92X for 15 users). • Memory issues: Does not fit in Internal Memory. • Real-time Requirements: Application Dependant. SR: 599 report

  23. Future Work • Effects on Downlink. • Effects of A/D Converter. • Tracking, Multiple sensors, Doppler effects. • Subspace Based Channel Estimation. • Real-time Performance. • Architectures for Wireless Communications. SR: 599 report

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