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Final Presentation

This final presentation discusses the use of prewritten twiddle factors in a ROM, with a focus on reducing ROM size and power consumption. The synthesis process, conclusion, and future work are also presented.

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Final Presentation

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  1. Group B3 B93901023 徐誠羿 B93901135 高翊軒 Mentor: Ben Final Presentation

  2. Structure Power issue Synthesis Conclusion Future Work Outline

  3. Radix22 Structure

  4. ROM Size Reduction Multiplier: Prewritten as a ROM. Reusing twiddle factors by symmetric character: => Reduce to 1/8 times as original ROM.

  5. Power Saving Issue Case(counter) Load: inf <= A8; Store: A7<=Out

  6. Synthesis Criterion: • Integer part: 3bits • Fractional part: 8bits • Twiddle factor: 10bits • When an adding process being executed, fractional part remains the same, and allocate one bit more for integer part. • SQNR=52dB

  7. Conclusion • Area Reduction: Reusing twiddle factors by symmetric character: => Reduce to 1/8 times as original ROM. Saving area by enlarging bit size step by step. • Power Reduction: Using pointers to avoid shifting registers. • Trade-off between time saving and area enhancement, vice versa.

  8. Future Work • Complete timing and area analysis. • Be more familiar with Verilog coding.

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