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Defense MicroElectronics Activity

Defense MicroElectronics Activity. The Impact of System Level Design on the DMS World. Keith Bergevin Senior Design Engineer 4234 54th St., Bldg. 620 Sacramento, CA. 95652-1521 Phone: (916) 231-1652, Fax: (916) 231- 2818 email: bergevin@dmea.osd.mil. VE00.06.01.

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Defense MicroElectronics Activity

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  1. Defense MicroElectronics Activity The Impact of System Level Design on the DMS World Keith Bergevin Senior Design Engineer 4234 54th St., Bldg. 620 Sacramento, CA. 95652-1521 Phone: (916) 231-1652, Fax: (916) 231- 2818 email: bergevin@dmea.osd.mil VE00.06.01

  2. Background: DesignMethodologies – What’s Next? • Pencil, Paper, Drafting Table • Quest for Computer Entry of Schematics • Schematic Capture • Quest for Faster, More Efficient Hardware Design Methods • Hardware Description Languages • Quest for Faster, More Efficient Design of Entire Systems

  3. Briefing Roadmap • What is System Level Design? • Benefits of System Level Design • Overview of Evolving System Level Design Languages • Impact of SLD on the DMS Community • DMEA’s Role in SLD

  4. What is System Level Design? • Today’s Systems Comprised of Multiple High-Density Components • Processors, RAM, ROM, I/O, ASICs, etc. • Each Component Separately Modeled, Simulated, & Designed • Various Methods used to Integrate Components into a System • System Level Design • One Specification to Model, Simulate, Synthesize all Functions • All Functions Integrated onto a Single Device called System-on-a-Chip (SoC)

  5. The Benefits of System Level Design (SLD) • Modeling of Entire System on a Chip (SoC) with a Single, Executable Specification • Hardware/Software Verification at an Earlier Stage • Concurrent H/W & S/W Design & Verification • Eliminate Intercommunication Translation Process • Traditionally, H/W Designed with VHDL or Verilog • S/W Designed with C/C++, Java, etc. • Large Overhead Incurred in Passing Data

  6. Leading System Level Design Languages • SystemC • Started with Technical Agreement and Development by Synopsys Inc., CoWare Inc., and Frontier Design Inc. • Extends C/C++ Language to Hardware and System Design • Freely Available through Open Source Licensing • Administered by Open SystemC Initiative (OSCI) Steering Group

  7. Leading System Level Design Languages • SystemC Primary Advantages: • Large Base of C/C++ Programmers • C/C++ Widely used to Model & Simulate Hardware • SystemC Primary Disadvantages: • Minimal Tools for Synthesis at this Time • C Language does not Support Notion of Time, Concurrency, Hardware Data Types, etc.

  8. Leading System Level Design Languages • Superlog • Superset of Verilog, with Addition of C Programming, System, & Verification Capabilities • Superlog Advantages • Large Base of Verilog Hardware Designers • Mature Synthesis Tools Available • Superlog Disadvantages • Requires Extensions to Achieve System Level Capabilities

  9. Leading System Level Design Languages • CynApps • Developed by CynApps Inc. Founded 1998 • C++ with Addition of Hardware Concurrency and Bit Accurate Data Types • CynApps Advantages • C++ Based • Models Hardware at All Levels of Abstraction • CynApps Disadvantages • Requires Translation to Verilog For Synthesis

  10. Impact of SLD from a DMS Standpoint • System-on-a-Chip (SoC) Design Magnifies Many DMS-Type Problems Currently Associated with ASIC Devices: • Replace with Alternate Source? • No. Custom Designs Virtually Ensure No Second Source Available • Re-Target? • Difficult. The First Generation of SoCs May Contain Combination of VHDL, Verilog, and one or more of the SLD Languages. • Reverse Engineer? • Extremely Difficult.

  11. DMEA’s Role in System Level Design and SoC Technology • Retain Step-for-Step Expertise in SoC with Industry • Imperative to Understand the Technology in Order to Develop DMS Solutions • Necessary to Understand SoC Technology in Order to Develop Guidelines for SoC Contractual Specifications • Continue to Strengthen Expertise in IP Core Design • Virtually all SoCs are Built via Integration of IP Cores • IP Core Re-Targeting is one of the few Cost-Effective Techniques Available • DMEA Flexible Foundry Provides Long-Term Support • Ensures Future Component Availability

  12. Summary • Technology Trends • Higher Density Custom Designs (SoCs) • New Generation of Hardware Description Languages • From a DMS Standpoint: No Easy Solutions • Sole Source Components • Difficult to Reverse Engineer • May be Difficult to Re-Target (Multiple Data Formats) • DMEA’s Approach to Mitigate Next Generation DMS Problems • Maintain State-of-the-Art Technical Skills • Continue Development of Cost-Effective Core Retargeting • Target Flexible Foundry Devices

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