1 / 11

AIDA design review Davide Braga Steve Thomas ASIC Design Group 11 February 2009

AIDA design review Davide Braga Steve Thomas ASIC Design Group 11 February 2009. External capacitors: crosstalk. The most sensitive biasing internal nodes have been identified and routed to a PAD to allow the use of external capacitors to stabilize those nets.

sue
Download Presentation

AIDA design review Davide Braga Steve Thomas ASIC Design Group 11 February 2009

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. AIDA design review Davide Braga Steve Thomas ASIC Design Group 11 February 2009

  2. External capacitors: crosstalk The most sensitive biasing internal nodes have been identified and routed to a PAD to allow the use of external capacitors to stabilize those nets. Is therefore possible to reduce both noise and crosstalk between different channels. The use of external capacitor on vcasc_preAmp reduces the crosstalk due to high energy implant in a different channel preAmpOut -no ext.cap preAmpOut - ext.cap shaperOut – no ext.cap shaperOut –ext.cap

  3. External capacitors: crosstalk Simulations including a resistor to model the equivalent resistance of bias tracks across the chip have not highlighted the need for two external capacitors for the same net at the two opposite sides of the chip. A full simulation of the parasitics though is too complex too run and it might be necessary to load critical nets on both sides if the test results suggest it.

  4. External capacitors: noise The noise performance is improved when the shaper’s reference is filtered with a big external capacitor (N.B: a 10Ω resistor is integrated on chip) Cext=1pF 1nF 1μF

  5. Power supply resistance (1) The power supply’s equivalent resistance could be a major source of crosstalk, simulation have been run to identify a maximum value for this resistance: In the first simplified model a resistance is placed between the ideal vdd (3.3V) and the effective one: looking at the shaper’s output of a non-active channel we can see that the effect of crosstalk increases together with the value of the resistor model1 model2

  6. vdd Ipower_supply(2 channel + bias block)

  7. Power supply resistance (1) Structures due to crosstalk appears on the shaper’s output when the power supply’ resistance is ~.1Ω RPowerSupply=0Ω 1mΩ 10mΩ 100mΩ 1Ω

  8. Power supply resistance (2) A second set of simulation models the resistance between the ASIC’s and the detector’s grounds: a spurious signal appears across the detector capacitance due to crosstalk via the power supply’s nets Charge across input coupling capacitor RPowerSupply=0Ω RPowerSupply=1mΩ RPowerSupply=10mΩ

  9. Power supply resistance (2) preAmplifier’s output

  10. Power supply resistance (2) Shaper’s output RPowerSupply=0Ω RPowerSupply=1mΩ RPowerSupply=10mΩ

  11. Conclusions Power supply tracking resistance on chip likely to be ~10mΩ Resistance off chip must be as small as possible, possible between 1mΩ to 10mΩ

More Related