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Design Review

Design Review. AVI1005 A1. Sean Wang. 2010/10/21. Item. Driver FET floor plans and layout sizes Bias Circuit Analysis with Equation Comparator Offset Analysis & Sensitivity to Tail Current Condition to Cause Initial Latch Problem & Solutions Hystersis Comparator to Replace Latch?

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Design Review

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  1. Design Review AVI1005 A1 Sean Wang 2010/10/21

  2. Item Driver FET floor plans and layout sizes Bias Circuit Analysis with Equation Comparator Offset Analysis & Sensitivity to Tail Current Condition to Cause Initial Latch Problem & Solutions Hystersis Comparator to Replace Latch? Chip simulation results (open-loop simulation) Rbias, Raout Determine VDS (Derive Equation) Loss of Power MOSFET Meas System, in Particular Base Noise

  3. 1. Driver FET floor plans and layout sizes Asy-PMOS Iso-Asy-NMOS 1000 um 1000 um 820 um 780 um Floor Plan 85um x 245um 180um x 250um Vcc GATE Pre-Driver PGND

  4. 2. Bias Circuit Analysis with Equation If VDD Variation

  5. 3.1 Comparator Offset Analysis & Sensitivity to Tail Current IMPD1 IMPD2 VSP1 VOUT VN VP

  6. 3.2 Comparator Offset Analysis & Sensitivity to Tail Current IMPD1 IMPD2 VSP1 VOUT VN VP

  7. 4.1 Condition to Cause Initial Latch Problem & Solutions Problem A. 假如使用Latch的方式，則在上述情況下，會發生Initial Latch的情形 Rising time is too slow

  8. 4.2 Condition to Cause Initial Latch Problem & Solutions Solution A. 讓AOUT的RisingTime加快 B. 設計電源進來時產生Blanking Time，時間內不判斷Aout訊號，並導通POWERMOS Use for improve rising time High Side : PMOS Use for Blanking

  9. 5. Hystersis Comparator to Replace Latch? • 考慮Drain電壓在DCM T3時會造成Ringing，使得AOUT = Vdrain x gm x Raout • AOUT變化過大，因此使用Hysister無法解決此現象 • B. 可考慮使用Latch或Blanking的方式，解決此問題

  10. 6. Chip simulation results (open-loop simulation) Zoon In VDRAIN dc 0.1V

  11. 7.1 Rext, Rint Determine VDS (Derive Equation)

  12. 8.1 Loss of Power MOSFET

  13. 8.2 Loss of Power MOSFET

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