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PARALLEL-SEARCH TRIE-BASED SCHEME FOR FAST IP LOOKUP

PARALLEL-SEARCH TRIE-BASED SCHEME FOR FAST IP LOOKUP. Author: Roberto Rojas-Cessa, Lakshmi Ramesh, Ziqian Dong, Lin Cai Nirwan Ansari Publisher: IEEE GLOBECOM 2007 Speaker: Han-Jhen Guo Date: 2008.09.02. OUTLINE. Parallel-Search Trie-Based Scheme Introduction Target levels Data structure

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PARALLEL-SEARCH TRIE-BASED SCHEME FOR FAST IP LOOKUP

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  1. PARALLEL-SEARCH TRIE-BASED SCHEME FOR FAST IP LOOKUP Author: Roberto Rojas-Cessa, Lakshmi Ramesh, Ziqian Dong, Lin Cai Nirwan Ansari Publisher: IEEE GLOBECOM 2007 Speaker: Han-Jhen Guo Date: 2008.09.02

  2. OUTLINE • Parallel-Search Trie-Based Scheme • Introduction • Target levels • Data structure • Implement • Search Procedure • Outline • Architecture and memory access • Longest prefix selection • Complexity and Performance • Conclusions

  3. PARALLEL-SEARCH TRIE-BASED SCHEME- INTRODUCTION (1/2) • forwarding table • binary trie

  4. PARALLEL-SEARCH TRIE-BASED SCHEME- INTRODUCTION (2/2) • expanded forwarding table • extended-prefix tree

  5. PARALLEL-SEARCH TRIE-BASED SCHEME- TARGET LEVELS (1/2) • select the target levels • IPv4 BGP Reports • Prefix Length Distributions • BGP data obtained from AS65000; Report last updated at Tue Sep 2 00:10:57 2008 (UTC+1000). • a large number of the prefixes are found between levels 16 and 24

  6. PARALLEL-SEARCH TRIE-BASED SCHEME- TARGET LEVELS (2/2) • 4 target levels (root level = 0) • bit vectors (global) • level 8 and 16 • segments (partial) • level 24 and 32

  7. PARALLEL-SEARCH TRIE-BASED SCHEME- DATA STRUCTURE (1/7) • nexthop information (15-bit) • one for each target level • scheme I: feasible amount of memory • associate every bit within a segment with a next-hop information without considering whether the prefix exists • scheme II: reduced memory • store the next-hop information for the positions where prefix exists • require one extra memory-access time if the longest prefix match is found on level 24 or 32

  8. PARALLEL-SEARCH TRIE-BASED SCHEME- DATA STRUCTURE (2/7) • example of level-8 and nexthop information

  9. PARALLEL-SEARCH TRIE-BASED SCHEME- DATA STRUCTURE (3/7) • level-8 • prefixVal (prefixVal8) • bitmap for prefix node (at level 8) • tableNext (tableNext8) • nexthop information for prefix node (at level 8)

  10. PARALLEL-SEARCH TRIE-BASED SCHEME- DATA STRUCTURE (4/7) • example of level-16

  11. PARALLEL-SEARCH TRIE-BASED SCHEME- DATA STRUCTURE (5/7) • level-16 • prefixVal(prefixVal16) • childVal (childVal24, childVal32) • indicates whether there is one or more prefixes of length between (17 and 24, 25 and 32) that share each 16-bit combination indexed by prefixVal16 • offsetVal (offsetVal16, offsetVal24, offsetVal32) • the total number of ones accumulated from all previous chunks • tableNext (tableNext16)

  12. PARALLEL-SEARCH TRIE-BASED SCHEME- DATA STRUCTURE (6/7) • example of level-24, level-32

  13. PARALLEL-SEARCH TRIE-BASED SCHEME- DATA STRUCTURE (7/7) • level-24 and 32 • prefixVal(prefixVal24, prefixVal32) • portInterval (portInterval24, portInterval32) • indicates the existence of the next hop information that is duplicated to reduce the number of port number memory • offsetPort (offsetPort24, offsetPort32) • indicates the number of prefixes that has next hop information in the previous segments of level (24, 32) • tableNext (tableNext24, tableNext32) • can use scheme II for economical

  14. IMPLEMENT • Separate blocks of memory for independent access

  15. SEARCH PROCEDURE (1/7)- OUTLINE • proposed trie-based IP lookup algorithm • at the first memory access, searches for a match in level 8 and 16 • in the second memory access, verifies possible matches at levels 24 and 32, and retrieves all possible next hops, one per level • If using reduced memory, the third time memory access is necessary for retrieves the nexthop information at levels 24 and 32. • if matches are achieved at different levels, the match belonging to the longest prefix is selected

  16. SEARCH PROCEDURE (2/7)- ARCHITECTURE AND MEMORY ACCESS (1/5) • 1st memory access

  17. SEARCH PROCEDURE (3/7)- ARCHITECTURE AND MEMORY ACCESS (2/5) • after 1st memory access

  18. SEARCH PROCEDURE (4/7)- ARCHITECTURE AND MEMORY ACCESS (3/5) • 2nd memory access

  19. SEARCH PROCEDURE (5/7)- ARCHITECTURE AND MEMORY ACCESS (4/5) • after 2nd memory access

  20. SEARCH PROCEDURE (6/7)- ARCHITECTURE AND MEMORY ACCESS (5/5) • 3rd memory access (only for reduced memory)

  21. SEARCH PROCEDURE (7/7)- LONGEST PREfiX SELECTION • Possibilities of matching prefixVal bit at different levels priority: low ←→ high

  22. COMPLEXITY AND PERFORMANCE (1/2) • Complexity

  23. COMPLEXITY AND PERFORMANCE (2/2) • Performance • routing table AS65000 (August 1, 2007) • number of entries: 82835 • average prefix length: 22 • number of segments for level 24: 6305 • number of segments for level 32: 82 • actual memory requirement • reduced memory scheme: 1.6 MB • feasible amount of memory scheme: 10 MB

  24. CONCLUSIONS

  25. Thanks for your listening!

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