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Compact Trie Forest: Scalable architecture for IP Lookup on FPGAs

Compact Trie Forest: Scalable architecture for IP Lookup on FPGAs. Author : O˘guzhan Erdem , Aydin Carus and Hoang Le Publisher : ReConFig 2012 Presenter : Yu Hao , Tzeng Date: 2013/2/20. Outline. Introduction Algorithm and Data Structure Architecture and Implementation on FPGA

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Compact Trie Forest: Scalable architecture for IP Lookup on FPGAs

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  1. Compact Trie Forest: Scalable architecture for IP Lookup on FPGAs Author: O˘guzhanErdem, AydinCarus and Hoang Le Publisher: ReConFig 2012 Presenter: Yu Hao, Tzeng Date: 2013/2/20

  2. Outline • Introduction • Algorithm and Data Structure • Architecture and Implementation on FPGA • Performance • Conclusion

  3. Introduction • Most hardware-based solutions for network routers • TCAM • DRAM / SRAM • FPGA • Compact Trie Forest • support up to 703K IPv4 and 418K IPv6 prefixes • sustain a throughput of 420 million lookups per second, or 135 Gbps for the minimum packet size of 40 Bytes

  4. Algorithm and Data Structure • Definitions and Notations • MSB ( Most Significant Bit ) • LSB ( Least Significant Bit ) • MSSB ( Most Significant Set Bit ) • LSSB ( Least Significant Set Bit ) • MSRB ( Most Significant Reset Bit ) • LSRB ( Least Significant Reset Bit ) • Example : 00110101* • 0 and 1 values as MSB and LSB • 2, 7, 0 and 6 values for MSSB, LSSB, MSRB and LSRB positions • Prefix Node • Non-Prefix Node

  5. Algorithm and Data Structure (Cont.) • Definitions and Notations • Active Part • MSSB and LSSB bits for (MSB, LSB) = (0, 0) • MSSB and LSRB bits for (MSB, LSB) = (0, 1) • MSRB and LSSB bits for (MSB, LSB) = (1, 0) • MSRB and LSRB bits for (MSB, LSB) = (1, 1) • Example A : 011011* • AP : 1 • Example B : 00101100* • AP : 01 • Conflicted Prefixes • For instance, the active part of 011001∗ and 0011010∗ are 10.

  6. Algorithm and Data Structure (Cont.) • Prefix Table Conversion • prefix p = xyz can be represented as a triplet {|x|, y, |z|} • For example, 000010010100∗ can be represented as {5, 0010∗, 3},

  7. Algorithm and Data Structure (Cont.) • Compact Trie Structure • In addition to the child pointers and the next hop information fields, extra information (|x|, |z|, MSB and LSB values) are stored at each node to differentiate the conflicted prefixes.

  8. Algorithm and Data Structure (Cont.) • Compact Trie Structure • set a limit for the number of conflicted prefixes per node Ptrie, and move the excessive conflicted prefixes to a newly generated CT

  9. Algorithm and Data Structure (Cont.) • IP Lookup Algorithm

  10. Algorithm and Data Structure (Cont.)

  11. Architecture and Implementation on FPGA

  12. Architecture and Implementation on FPGA (Cont. )

  13. Performance

  14. Conclusion • Therefore, the algorithm can be used to improve the performance (throughput and memory efficiency) of trie-based IPv4/v6 lookup schemes to satisfy fast internet link rates up to and beyond 100 Gbps at core routers, and compact memory footprint that can fit in the on-chip caches of multi-core and network processors.

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