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Report on PXD Session

Report on PXD Session. Overview on pixel layer requirements (G. Varner, Hawaii). Overview on pixel layer requirements (G. Varner, Hawaii). Overview on pixel layer requirements (G. Varner, Hawaii). Overview on pixel layer requirements (G. Varner, Hawaii).

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Report on PXD Session

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  1. Report on PXD Session

  2. Overview on pixel layer requirements (G. Varner, Hawaii)

  3. Overview on pixel layer requirements (G. Varner, Hawaii)

  4. Overview on pixel layer requirements (G. Varner, Hawaii)

  5. Overview on pixel layer requirements (G. Varner, Hawaii)

  6. Overview on pixel layer requirements (G. Varner, Hawaii)

  7. Overview on pixel layer requirements (G. Varner, Hawaii)

  8. Pixel Simulations (A. Frey, Munich)

  9. Pixel Simulations (A. Frey, Munich) Proposal: Consider Mokka framework (Geant4) for general superBelle MC

  10. Pixel Simulations (A. Frey, Munich)

  11. Pixel Simulations (A. Frey, Munich)

  12. DEPFET Technology (A. Andricek, Munich)

  13. DEPFET Technology (A. Andricek, Munich)

  14. DEPFET Technology (A. Andricek, Munich)

  15. DEPFET Technology (A. Andricek, Munich) ASICs: DCD and Switcher are deep submicron technologies  rad. hard beyond 10Mrad (with the appropriate design) DEPFETs: Not that easy …  … noise performance seems to be okay up to 8 Mrad threshold shift could be compensated by re-adjustment of the Switcher voltages ∆Vt variation at higher TID (reason for this under investigation) and hence ∆ID at a given VGate has to be compensated by the DCD  slightly higher noise of the f/e technological counter measures: thinner gate oxide reduces |∆Vt| further optimization of the gate dielectrics In conclusion: The DEPFET gets worse at high TIDs (8Mrad). Probably ok for several years of running

  16. DEPFET Technology (A. Andricek, Munich) Thinning technology established 50 mm + frame All silicon ~0.14% X0 (average) Collaboration forming First superBelle prototypes 2010 (PXD5) Schedule to build complete detector till 2013

  17. SOI Technology (T. Tsuboyama, KEK)

  18. SOI Technology (T. Tsuboyama, KEK) 49 Mrad! Typical problem: Back gate effect Chip submitted, still waiting Similar project by Hawaii (same submission)

  19. CMOS Technology (G. Varner, Hawaii)

  20. CMOS Technology (G. Varner, Hawaii)

  21. CMOS Technology (G. Varner, Hawaii)

  22. Data Rate & DAQ(C. Lacasta, Valencia)

  23. Data Rate & DAQ(C. Lacasta, Valencia) Gbit/s

  24. New Technologies: 3D Ron Lipton (Plenary)

  25. New Technologies: 3D Ron Lipton (Plenary) • Test run with MIT: • VIP chip: 3 layer, no sensor • Low yield, many problems • Proof of principle! Continue with Tezzaron/Ziptonix • Powerful technology Time stamp DT = 300 ns: 1/33 reduction of Occupancy!

  26. Conclusions Pixel Detector for SuperBelle should: allow robust vertexing at high background improve performance with respect to SVD2 => fast readout (or time stamp), thin Technologies: DEPFET SOI CMOS-MAPS 3D-technologie Aiming for installation in 2013 the DEPFET option seems to be the most realisitc (ok for running ~years at initial luminosity) => Tight schedule: start now! For final luminosity: consider ALL options

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